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(1 - 10 of 10)
- Title
- REALIZATION OF POWER FACTOR CORRECTION AND MAXIMUM POWER POINT TRACKING FOR LOW POWER WIND TURBINES.
- Creator
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Gamboa, Gustavo, Batarseh, Issa, University of Central Florida
- Abstract / Description
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In recent years, wind energy technology has become one of the top areas of interest for energy harvesting in the power electronics world. This interest has especially peaked recently due to the increasing demand for a reliable source of renewable energy. In a recent study, the American Wind Energy Association (AWEA) ranked the U.S as the leading competitor in wind energy harvesting followed by Germany and Spain. Although the United States is the leading competitor in this area, no one has...
Show moreIn recent years, wind energy technology has become one of the top areas of interest for energy harvesting in the power electronics world. This interest has especially peaked recently due to the increasing demand for a reliable source of renewable energy. In a recent study, the American Wind Energy Association (AWEA) ranked the U.S as the leading competitor in wind energy harvesting followed by Germany and Spain. Although the United States is the leading competitor in this area, no one has been able successfully develop an efficient, low-cost AC/DC convertor for low power turbines to be used by the average American consumer. There has been very little research in low power AC/DC converters for low to medium power wind energy turbines for battery charging applications. Due to the low power coefficient of wind turbines, power converters are required to transfer the maximum available power at the highest efficiency. Power factor correction (PFC) and maximum power point tracking (MPPT) algorithms have been proposed for high power wind turbines. These turbines are out of the price range of what a common household can afford. They also occupy a large amount of space, which is not practical for use in one's home. A low cost AC/DC converter with efficient power transfer is needed in order to promote the use of cheaper low power wind turbines. Only MPPT is implemented in most of these low power wind turbine power converters. The concept of power factor correction with MPPT has not been completely adapted just yet. The research conducted involved analyzing the effect of power factor correction and maximum power point tracking algorithm in AC/DC converters for wind turbine applications. Although maximum power to the load is always desired, most converters only take electrical efficiency into consideration. However, not only the electrical efficiency must be considered, but the mechanical energy as well. If the converter is designed to look like a purely resistive load and not a switched load, a wind turbine is able to supply the maximum power with lower conduction loss at the input side due to high current spikes. Two power converters, VIENNA with buck converter and a Buck-boost converter, were designed and experimentally analyzed. A unique approach of controlling the MPPT algorithm through a conductance G for PFC is proposed and applied in the VIENNA topology. On the other hand, the Buck-boost only operates MPPT. With the same wind profile applied for both converters, an increase in power drawn from the input increased when PFC was used even when the power level was low. Both topologies present their own unique advantages. The main advantage for the VIENNA converter is that PFC allowed more power extraction from the turbine, increasing both electrical and mechanical efficiency. The buck-boost converter, on the other hand, presents a very low component count which decreases the overall cost and volume. Therefore, a small, cost-effective converter that maximizes the power transfer from a small power wind turbine to a DC load, can motivate consumers to utilize the power available from the wind.
Show less - Date Issued
- 2009
- Identifier
- CFE0002730, ucf:48158
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0002730
- Title
- LDMOS Power Transistor Design and Evaluation using 2D and 3D Device Simulation.
- Creator
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Salih, Aiman, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Kapoor, Vikram, University of Central Florida
- Abstract / Description
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The benefit of the super-junction (SJ) technique and the use of a floating P layer for low voltage (30 V) laterally double-diffused metal oxide semiconductor (LDMOS) transistors are investigated in this thesis using Sentaurus TCAD simulation software. Optimizations to the SJ LDMOS were attempted such as adding a buffer layer to the device, but simulation and theoretical evidence point out that the benefits of the SJ technique are marginal at the 30 V application. A replacement for the SJ...
Show moreThe benefit of the super-junction (SJ) technique and the use of a floating P layer for low voltage (30 V) laterally double-diffused metal oxide semiconductor (LDMOS) transistors are investigated in this thesis using Sentaurus TCAD simulation software. Optimizations to the SJ LDMOS were attempted such as adding a buffer layer to the device, but simulation and theoretical evidence point out that the benefits of the SJ technique are marginal at the 30 V application. A replacement for the SJ technique was sought, the floating P structure proved to be a good solution at the low voltage range due to its simpler cost effective process and performance gains achieved with optimization. A new idea of combining the floating P layer with shallow trench isolation is simulated yielding a low figure of merit (on state resistance (&)#215; gate charge) of 5.93 m?-nC.
Show less - Date Issued
- 2017
- Identifier
- CFE0006955, ucf:51673
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0006955
- Title
- LOW POWER CMOS CIRCUIT DESIGN AND RELIABILITY ANALYSIS FOR WIRELESS MEMS SENSORS.
- Creator
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Sadat, Md Anwar, Yuan, Jiann, University of Central Florida
- Abstract / Description
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A sensor node 'AccuMicroMotion' is proposed that has the ability to detect motion in 6 degrees of freedom for the application of physiological activity monitoring. It is expected to be light weight, low power, small and cheap. The sensor node may collect and transmit 3 axes of acceleration and 3 axes of angular rotation signals from MEMS transducers wirelessly to a nearby base station while attached to or implanted in human body. This dissertation proposes a wireless electronic system-on-a...
Show moreA sensor node 'AccuMicroMotion' is proposed that has the ability to detect motion in 6 degrees of freedom for the application of physiological activity monitoring. It is expected to be light weight, low power, small and cheap. The sensor node may collect and transmit 3 axes of acceleration and 3 axes of angular rotation signals from MEMS transducers wirelessly to a nearby base station while attached to or implanted in human body. This dissertation proposes a wireless electronic system-on-a-single-chip to implement the sensor in a traditional CMOS process. The system is low power and may operate 50 hours from a single coin cell battery. A CMOS readout circuit, an analog to digital converter and a wireless transmitter is designed to implement the proposed system. In the architecture of the 'AccuMicroMotion' system, the readout circuit uses chopper stabilization technique and can resolve DC to 1 KHz and 200 nV signals from MEMS transducers. The base band signal is digitized using a 10-bit successive approximation register analog to digital converter. Digitized outputs from up to nine transducers can be combined in a parallel to serial converter for transmission by a 900 MHz RF transmitter that operates in amplitude shift keying modulation technique. The transmitter delivers a 2.2 mW power to a 50 Ù antenna. The system consumes an average current of 4.8 mA from a 3V supply when 6 sensors are in operation and provides an overall 60 dB dynamic range. Furthermore, in this dissertation, a methodology is developed that applies accelerated electrical stress on MOS devices to extract BSIM3 models and RF parameters through measurements to perform comprehensive study, analysis and modeling of several analog and RF circuits under hot carrier and breakdown degradation.
Show less - Date Issued
- 2004
- Identifier
- CFE0000304, ucf:46318
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0000304
- Title
- GaN Power Devices: Discerning Application-Specific Challenges and Limitations in HEMTs.
- Creator
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Binder, Andrew, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Roy, Tania, Kapoor, Vikram, Chow, Lee, University of Central Florida
- Abstract / Description
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GaN power devices are typically used in the 600 V market, for high efficiency, high power-density systems. For these devices, the lateral optimization of gate-to-drain, gate, and gate-to-source lengths, as well as gate field-plate length are critical for optimizing breakdown voltage and performance. This work presents a systematic study of lateral scaling optimization for high voltage devices to minimize figure of merit and maximize breakdown voltage. In addition, this optimization is...
Show moreGaN power devices are typically used in the 600 V market, for high efficiency, high power-density systems. For these devices, the lateral optimization of gate-to-drain, gate, and gate-to-source lengths, as well as gate field-plate length are critical for optimizing breakdown voltage and performance. This work presents a systematic study of lateral scaling optimization for high voltage devices to minimize figure of merit and maximize breakdown voltage. In addition, this optimization is extended for low voltage devices ((<) 100 V), presenting results to optimize both lateral features and vertical features. For low voltage design, simulation work suggests that breakdown is more reliant on punch-through as the primary breakdown mechanism rather than on vertical leakage current as is the case with high-voltage devices. A fabrication process flow has been developed for fabricating Schottky-gate, and MIS-HEMT structures at UCF in the CREOL cleanroom. The fabricated devices were designed to validate the simulation work for low voltage GaN devices. The UCF fabrication process is done with a four layer mask, and consists of mesa isolation, ohmic recess etch, an optional gate insulator layer, ohmic metallization, and gate metallization. Following this work, the fabrication process was transferred to the National Nano Device Laboratories (NDL) in Hsinchu, Taiwan, to take advantage of the more advanced facilities there. Following fabrication, a study has been performed on defect induced performance degradation, leading to the observation of a new phenomenon: trap induced negative differential conductance (NDC). Typically NDC is caused by self-heating, however by implementing a substrate bias test in conjunction with pulsed I-V testing, the NDC seen in our fabricated devices has been confirmed to be from buffer traps that are a result of poor channel carrier confinement during the dc operating condition.
Show less - Date Issued
- 2019
- Identifier
- CFE0007885, ucf:52786
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0007885
- Title
- DESIGNING LIGHT FILTERS TO DETECT SKIN USING A LOW-POWERED SENSOR.
- Creator
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Tariq, Muhammad, Wisniewski, Pamela, Gong, Boqing, Leavens, Gary, University of Central Florida
- Abstract / Description
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Detection of nudity in photos and videos, especially prior to uploading to the internet, is vital to solving many problems related to adolescent sexting, the distribution of child pornography, and cyber-bullying. The problem with using nudity detection algorithms as a means to combat these problems is that: 1) it implies that a digitized nude photo of a minor already exists (i.e., child pornography), and 2) there are real ethical and legal concerns around the distribution and processing of...
Show moreDetection of nudity in photos and videos, especially prior to uploading to the internet, is vital to solving many problems related to adolescent sexting, the distribution of child pornography, and cyber-bullying. The problem with using nudity detection algorithms as a means to combat these problems is that: 1) it implies that a digitized nude photo of a minor already exists (i.e., child pornography), and 2) there are real ethical and legal concerns around the distribution and processing of child pornography. Once a camera captures an image, that image is no longer secure. Therefore, we need to develop new privacy-preserving solutions that prevent the digital capture of nude imagery of minors. My research takes a first step in trying to accomplish this long-term goal: In this thesis, I examine the feasibility of using a low-powered sensor to detect skin dominance (defined as an image comprised of 50% or more of human skin tone) in a visual scene. By designing four custom light filters to enhance the digital information extracted from 300 scenes captured with the sensor (without digitizing high-fidelity visual features), I was able to accurately detect a skin dominant scene with 83.7% accuracy, 83% precision, and 85% recall. The long-term goal to be achieved in the future is to design a low-powered vision sensor that can be mounted on a digital camera lens on a teen's mobile device to detect and/or prevent the capture of nude imagery. Thus, I discuss the limitations of this work toward this larger goal, as well as future research directions.
Show less - Date Issued
- 2017
- Identifier
- CFE0006806, ucf:51792
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0006806
- Title
- HIGH CURRENT DENSITY LOW VOLTAGE ISOLATED DC-DC CONVERTERSWITH FAST TRANSIENT RESPONSE.
- Creator
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Yao, Liangbin, Batarseh, Issa, University of Central Florida
- Abstract / Description
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With the rapid development of microprocessor and semiconductor technology, industry continues to update the requirements for power supplies. For telecommunication and computing system applications, power supplies require increasing current level while the supply voltage keeps decreasing. For example, the Intel's CPU core voltage decreased from 2 volt in 1999 to 1 volt in 2005 while the supply current increased from 20A in 1999 to up to 100A in 2005. As a result, low-voltage high-current...
Show moreWith the rapid development of microprocessor and semiconductor technology, industry continues to update the requirements for power supplies. For telecommunication and computing system applications, power supplies require increasing current level while the supply voltage keeps decreasing. For example, the Intel's CPU core voltage decreased from 2 volt in 1999 to 1 volt in 2005 while the supply current increased from 20A in 1999 to up to 100A in 2005. As a result, low-voltage high-current high efficiency dc-dc converters with high power-density are demanded for state-of-the-art applications and also the future applications. Half-bridge dc-dc converter with current-doubler rectification is regarded as a good topology that is suitable for high-current low-voltage applications. There are three control schemes for half-bridge dc-dc converters and in order to provide a valid unified analog model for optimal compensator design, the analog state-space modeling and small signal modeling are studied in the dissertation and unified state-space and analog small signal model are derived. In addition, the digital control gains a lot of attentions due to its flexibility and re-programmability. In this dissertation, a unified digital small signal model for half-bridge dc-dc converter with current doubler rectifier is also developed and the digital compensator based on the derived model is implemented and verified by the experiments with the TI DSP chip. In addition, although current doubler rectifier is widely used in industry, the key issue is the current sharing between two inductors. The current imbalance is well studied and solved in non-isolated multi-phase buck converters, yet few discusse this issue in the current doubler rectification topology within academia and industry. This dissertation analyze the current sharing issue in comparison with multi-phase buck and one modified current doubler rectifier topology is proposed to achieve passive current sharing. The performance is evaluated with half bridge dc-dc converter; good current sharing is achieved without additional circuitry. Due to increasing demands for high-efficiency high-power-density low-voltage high current topologies for future applications, the thermal management is challenging. Since the secondary-side conduction loss dominates the overall power loss in low-voltage high-current isolated dc-dc converters, a novel current tripler rectification topology is proposed. Theoretical analysis, comparison and experimental results verify that the proposed rectification technique has good thermal management and well-distributed power dissipation, simplified magnetic design and low copper loss for inductors and transformer. That is due to the fact that the load current is better distributed in three inductors and the rms current in transformer windings is reduced. Another challenge in telecommunication and computing applications is fast transient response of the converter to the increasing slew-rate of load current change. For instance, from Intel's roadmap, it can be observed that the current slew rate of the age regulator has dramatically increased from 25A/uS in 1999 to 400A/us in 2005. One of the solutions to achieve fast transient response is secondary-side control technique to eliminate the delay of optocoupler to increase the system bandwidth. Active-clamp half bridge dc-dc converter with secondary-side control is presented and one industry standard 16th prototype is built and tested; good efficiency and transient response are shown in the experimental section. However, one key issue for implementation of secondary-side control is start-up. A new zero-voltage-switching buck-flyback isolated dc-dc converter with synchronous rectification is proposed, and it is only suitable for start-up circuit for secondary-side controlled converter, but also for house-keeping power supplies and standalone power supplies requiring multi-outputs.
Show less - Date Issued
- 2007
- Identifier
- CFE0001814, ucf:47336
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0001814
- Title
- Normally-Off Computing Design Methodology Using Spintronics: from Devices to Architectures.
- Creator
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Roohi, Arman, DeMara, Ronald, Abdolvand, Reza, Wang, Jun, Fan, Deliang, Del Barco, Enrique, University of Central Florida
- Abstract / Description
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Energy-harvesting-powered computing offers intriguing and vast opportunities to dramatically transform the landscape of Internet of Things (IoT) devices and wireless sensor networks by utilizing ambient sources of light, thermal, kinetic, and electromagnetic energy to achieve battery-free computing. In order to operate within the restricted energy capacity and intermittency profile of battery-free operation, it is proposed to innovate Elastic Intermittent Computation (EIC) as a new duty-cycle...
Show moreEnergy-harvesting-powered computing offers intriguing and vast opportunities to dramatically transform the landscape of Internet of Things (IoT) devices and wireless sensor networks by utilizing ambient sources of light, thermal, kinetic, and electromagnetic energy to achieve battery-free computing. In order to operate within the restricted energy capacity and intermittency profile of battery-free operation, it is proposed to innovate Elastic Intermittent Computation (EIC) as a new duty-cycle-variable computing approach leveraging the non-volatility inherent in post-CMOS switching devices. The foundations of EIC will be advanced from the ground up by extending Spin Hall Effect Magnetic Tunnel Junction (SHE-MTJ) device models to realize SHE-MTJ-based Majority Gate (MG) and Polymorphic Gate (PG) logic approaches and libraries, that leverage intrinsic-non-volatility to realize middleware-coherent, intermittent computation without checkpointing, micro-tasking, or software bloat and energy overheads vital to IoT. Device-level EIC research concentrates on encapsulating SHE-MTJ behavior with a compact model to leverage the non-volatility of the device for intrinsic provision of intermittent computation and lifetime energy reduction. Based on this model, the circuit-level EIC contributions will entail the design, simulation, and analysis of PG-based spintronic logic which is adaptable at the gate-level to support variable duty cycle execution that is robust to brief and extended supply outages or unscheduled dropouts, and development of spin-based research synthesis and optimization routines compatible with existing commercial toolchains. These tools will be employed to design a hybrid post-CMOS processing unit utilizing pipelining and power-gating through state-holding properties within the datapath itself, thus eliminating checkpointing and data transfer operations.
Show less - Date Issued
- 2019
- Identifier
- CFE0007526, ucf:52619
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0007526
- Title
- Towards Energy-Efficient and Reliable Computing: From Highly-Scaled CMOS Devices to Resistive Memories.
- Creator
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Salehi Mobarakeh, Soheil, DeMara, Ronald, Fan, Deliang, Turgut, Damla, University of Central Florida
- Abstract / Description
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The continuous increase in transistor density based on Moore's Law has led us to highly scaled Complementary Metal-Oxide Semiconductor (CMOS) technologies. These transistor-based process technologies offer improved density as well as a reduction in nominal supply voltage. An analysis regarding different aspects of 45nm and 15nm technologies, such as power consumption and cell area to compare these two technologies is proposed on an IEEE 754 Single Precision Floating-Point Unit implementation....
Show moreThe continuous increase in transistor density based on Moore's Law has led us to highly scaled Complementary Metal-Oxide Semiconductor (CMOS) technologies. These transistor-based process technologies offer improved density as well as a reduction in nominal supply voltage. An analysis regarding different aspects of 45nm and 15nm technologies, such as power consumption and cell area to compare these two technologies is proposed on an IEEE 754 Single Precision Floating-Point Unit implementation. Based on the results, using the 15nm technology offers 4-times less energy and 3-fold smaller footprint. New challenges also arise, such as relative proportion of leakage power in standby mode that can be addressed by post-CMOS technologies. Spin-Transfer Torque Random Access Memory (STT-MRAM) has been explored as a post-CMOS technology for embedded and data storage applications seeking non-volatility, near-zero standby energy, and high density. Towards attaining these objectives for practical implementations, various techniques to mitigate the specific reliability challenges associated with STT-MRAM elements are surveyed, classified, and assessed herein. Cost and suitability metrics assessed include the area of nanomagmetic and CMOS components per bit, access time and complexity, Sense Margin (SM), and energy or power consumption costs versus resiliency benefits. In an attempt to further improve the Process Variation (PV) immunity of the Sense Amplifiers (SAs), a new SA has been introduced called Adaptive Sense Amplifier (ASA). ASA can benefit from low Bit Error Rate (BER) and low Energy Delay Product (EDP) by combining the properties of two of the commonly used SAs, Pre-Charge Sense Amplifier (PCSA) and Separated Pre-Charge Sense Amplifier (SPCSA). ASA can operate in either PCSA or SPCSA mode based on the requirements of the circuit such as energy efficiency or reliability. Then, ASA is utilized to propose a novel approach to actually leverage the PV in Non-Volatile Memory (NVM) arrays using Self-Organized Sub-bank (SOS) design. SOS engages the preferred SA alternative based on the intrinsic as-built behavior of the resistive sensing timing margin to reduce the latency and power consumption while maintaining acceptable access time.
Show less - Date Issued
- 2016
- Identifier
- CFE0006493, ucf:51400
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0006493
- Title
- CMOS RF CITUITS VARIABILITY AND RELIABILITY RESILIENT DESIGN, MODELING, AND SIMULATION.
- Creator
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Liu, Yidong, Yuan, Jiann-Shiun, University of Central Florida
- Abstract / Description
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The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm...
Show moreThe work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm technology is adopted in modeling the transistors within these RF blocks. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. The results show that the biasing design helps improve the robustness of the PA in terms of linear gain, P1dB, Psat, and power added efficiency (PAE). Except for post-fabrication calibration capability, the design reduces the majority performance sensitivity of PA by 50% when subjected to threshold voltage (VT) shift and 25% to electron mobility (¼n) degradation. The impact of degradation mismatches is also investigated. It is observed that the accelerated aging of MOS transistor in the biasing circuit will further reduce the sensitivity of PA. In the study of LNA, a 24 GHz narrow band cascade LNA with adaptive biasing scheme under various aging rate is compared to LNA without such biasing scheme. The modeling and simulation results show that the adaptive substrate biasing reduces the sensitivity of noise figure and minimum noise figure subject to process variation and device aging such as threshold voltage shift and electron mobility degradation. Simulation of different aging rate also shows that the sensitivity of LNA is further reduced with the accelerated aging of the biasing circuit. Thus, for majority RF transceiver circuits, the adaptive body biasing scheme provides overall performance resilience to the device reliability induced degradation. Also the tuning ability designed in RF PA and LNA provides the circuit post-process calibration capability.
Show less - Date Issued
- 2011
- Identifier
- CFE0003595, ucf:48861
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0003595
- Title
- Reexamining the Relationship Between Divided Government and Voter Turnout.
- Creator
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Beck, Heidi, Knuckey, Jonathan, Jewett, Aubrey, Lanier, Drew, University of Central Florida
- Abstract / Description
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This thesis reexamines the effect of divided government on voter turnout originally posited byFranklin and Hirczy de Mi(&)#241;o (1998), which suggested that each year of exposure to dividedgovernment resulted in a cumulative negative effect on voters leading to alienation and lowerturnout. It reconsiders this argument using more recent data, given that voter turnout in U.S.presidential elections (as measured by the Voting Eligible Population) has increased since 2000,even though divided...
Show moreThis thesis reexamines the effect of divided government on voter turnout originally posited byFranklin and Hirczy de Mi(&)#241;o (1998), which suggested that each year of exposure to dividedgovernment resulted in a cumulative negative effect on voters leading to alienation and lowerturnout. It reconsiders this argument using more recent data, given that voter turnout in U.S.presidential elections (as measured by the Voting Eligible Population) has increased since 2000,even though divided government has occurred during this period.This thesis also uses new data and methods to address concerns about the original aggregatelevelresearch design. The research question is tested at the individual-level of analysis todetermine if divided government does interact with political trust to lower turnout. Previousresearch assumed this relationship since there is no aggregate-level proxy for political trust. Byusing survey data from the American National Election Studies it is now possible to test the fulltheory.The aggregate-level models show that misspecifications in the research design of Franklinand Hirczy de Mi(&)#241;o resulting in multicollinearity, and in two instances autocorrelation, whichresulted in a failure to reject the null hypothesis. The individual-level models show that dividedgovernment interacts with low levels of political trust to increase voter turnout, falsifying theargument about the effect of divided government on turnout. Overall, the thesis suggests that theimplications of an aspect of the American political system that renders it distinguishable frommost other advanced-industrial democracies(-)divided party control of the executive andlegislative branches(-)should be reassessed. More generally, the thesis demonstrates theimportance of reevaluating hypotheses in political science with the most recent data and morerobust methods in order to establish whether those original hypotheses are still supported
Show less - Date Issued
- 2019
- Identifier
- CFE0007783, ucf:52363
- Format
- Document (PDF)
- PURL
- http://purl.flvc.org/ucf/fd/CFE0007783
