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Title: STUDY OF ESD EFFECTS ON RF POWER AMPLIFIERS.
Creator: Narasimha Raju, Divya, Yuan, Jiann, University of Central Florida
Abstract / Description: Today, ESD is a major consideration in the design and manufacture of ICs. ESD problems are increasing in the electronics industry because of the increasing trend toward higher speed and smaller device sizes. There is growing interest in knowing the effects of ESD protection circuit on the performance of semiconductor integrated circuits (ICs) because of the impact it has on core RF circuit performance. This study investigated the impact of ESD protection circuit on RF Power amplifiers. Even...
Show moreToday, ESD is a major consideration in the design and manufacture of ICs. ESD problems are increasing in the electronics industry because of the increasing trend toward higher speed and smaller device sizes. There is growing interest in knowing the effects of ESD protection circuit on the performance of semiconductor integrated circuits (ICs) because of the impact it has on core RF circuit performance. This study investigated the impact of ESD protection circuit on RF Power amplifiers. Even though ESD protection for digital circuits has been known for a while, RF-ESD is a challenge. From a thorough literature search on prior art ESD protection circuits, Silicon controlled rectifier was found to be most effective and reliable ESD protection for power amplifier circuit. A SCR based ESD protection was used to protect the power amplifier and a model was developed to gain better understanding of ESD protected power amplifiers. Simulated results were compared and contrasted against theoretically derived equations. A 5.2GHz fully ESD protected Class AB power amplifier was designed and simulated using TSMC 0.18 um technology. Further, the ESD protection circuit was added to a cascoded Class-E power amplifier operating at 5.2 GHz. ADS simulation results were used to analyze the PA's RF performance degradation. Various optimization techniques were used to improve the RF circuit performance.
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Date Issued: 2011
Identifier: CFE0003630, ucf:48881
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003630

Title: PROTOTYPE OF COUPLING UNIT NETWORK FOR POWER LINE COMMUNICATIONS.
Creator: Srinivasan, Bharath, Wei, Lei, University of Central Florida
Abstract / Description: Power Line Communications has made impressive strides since its introduction. Power Line Communications (PLC) or Broadband over Power Lines (BPL) is the method of transmitting broadband signals over the power lines and making it available at the power outlet in homes. It provides last mile communication and makes use of existing power lines to transmit signals, thereby eliminating the need to lay cables all over again. PLC is fast becoming a commercial reality in the United States. The...
Show morePower Line Communications has made impressive strides since its introduction. Power Line Communications (PLC) or Broadband over Power Lines (BPL) is the method of transmitting broadband signals over the power lines and making it available at the power outlet in homes. It provides last mile communication and makes use of existing power lines to transmit signals, thereby eliminating the need to lay cables all over again. PLC is fast becoming a commercial reality in the United States. The Federal Communications Commission (FCC) is working toward making PLC a standard with particular emphasis on power emission issues and interference with nearby bands. Power companies, vendors and ISPs (Internet Service Providers) have tied up to bring this new technology to market. The Power line environment is inherently unpredictable due to interference, low signaling impedance and the highly linear operating environment that PLC transmitters require. The coupling unit in the PLC system acts as a filter and eliminates the harmful AC signal from interfering with the broadband signals. A coupling unit amplifier topology that provides gain equalization and wideband mitigation to the effects of low-impedance loads on PLC in the high frequency range has been explored in detail in this study. The amplifier is verified for its performance by means of circuit simulation using industry-standard software such as Agilent's Advanced Design System (ADS). The coupling unit has also been fabricated to verify the performance. An experimental setup for verifying the performance of the coupling unit using a PLC transmitter and PLC receiver has also been proposed.
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Date Issued: 2006
Identifier: CFE0001306, ucf:47029
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0001306

Title: Peak Power Scaling of Nanosecond Pulses in Thulium based Fiber Lasers.
Creator: Gaida, Christian, Richardson, Martin, Shah, Lawrence, Amezcua Correa, Rodrigo, University of Central Florida
Abstract / Description: Thulium based fiber lasers represent a promising alternative for pulse energy scaling and highpeak power generation with ytterbium based systems at 1 micrometer. Advantages of thulium arise fromthe operation at longer wavelengths and a large gain bandwidth (1.8-2.1 micrometer). Nonlinear effects,such as self phase modulation, stimulated Raman scattering and stimulated Brillouin scattering generally limit peak power scaling in fiber lasers. The longer wavelength of thulium fiber lasersand...
Show moreThulium based fiber lasers represent a promising alternative for pulse energy scaling and highpeak power generation with ytterbium based systems at 1 micrometer. Advantages of thulium arise fromthe operation at longer wavelengths and a large gain bandwidth (1.8-2.1 micrometer). Nonlinear effects,such as self phase modulation, stimulated Raman scattering and stimulated Brillouin scattering generally limit peak power scaling in fiber lasers. The longer wavelength of thulium fiber lasersand large mode field areas can significantly increase the nonlinear thresholds. Compared to 1 micrometer systems, thulium fiber lasers enable single mode guidance for two times larger mode field diameterin step index fibers. Similar behavior is expected for index guiding thulium doped photonic crystalfibers.In this work a novel thulium doped rod type photonic crystal fiber design with large mode field diameter (>50 micrometer) was first characterized in CW-lasing configuration and then utilized as finalamplifier in a two stage master oscillator power amplifier. The system generated MW-level peakpower at 6.5ns pulse duration and 1kHz repetition rate. This world record performance exemplifiesthe potential of thulium fiber lasers to supersede ytterbium based systems for very high peak powergeneration in the future.As part of this work a computer model for the transient simulation of pulsed amplification inthulium based fiber lasers was developed. The simulations are in good agreement with the experimentalresults. The computer model can be used for efficient optimization of future thulium basedfiber amplifier designs.
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Date Issued: 2013
Identifier: CFE0004845, ucf:49699
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0004845

Title: STUDY OF DESIGN FOR RELIABILITY OF RF AND ANALOG CIRCUITS.
Creator: Tang, Hongxia, Yuan, Jiann-Shiun, Wu, Xinzhang, Sundaram, Kalpathy, Chow, Lee, University of Central Florida
Abstract / Description: Due to continued device dimensions scaling, CMOS transistors in the nanometer regime have resulted in major reliability and variability challenges. Reliability issues such as channel hot electron injection, gate dielectric breakdown, and negative bias temperature instability (NBTI) need to be accounted for in the design of robust RF circuits. In addition, process variations in the nanoscale CMOS transistors are another major concern in today's circuits design.An adaptive gate-source biasing...
Show moreDue to continued device dimensions scaling, CMOS transistors in the nanometer regime have resulted in major reliability and variability challenges. Reliability issues such as channel hot electron injection, gate dielectric breakdown, and negative bias temperature instability (NBTI) need to be accounted for in the design of robust RF circuits. In addition, process variations in the nanoscale CMOS transistors are another major concern in today's circuits design.An adaptive gate-source biasing scheme to improve the RF circuit reliability is presented in this work. The adaptive method automatically adjusts the gate-source voltage to compensate the reduction in drain current subjected to various device reliability mechanisms. A class-AB RF power amplifier shows that the use of a source resistance makes the power-added efficiency robust against threshold voltage and mobility variations, while the use of a source inductance is more reliable for the input third-order intercept point.A RF power amplifier with adaptive gate biasing is proposed to improve the circuit device reliability degradation and process variation. The performances of the power amplifier with adaptive gate biasing are compared with those of the power amplifier without adaptive gate biasing technique. The adaptive gate biasing makes the power amplifier more resilient to process variations as well as the device aging such as mobility and threshold voltage degradation. Injection locked voltage-controlled oscillators (VCOs) have been examined. The VCOs are implemented using TSMC 0.18 (&)#181;m mixed-signal CMOS technology. The injection locked oscillators have improved phase noise performance than free running oscillators.A differential Clapp-VCO has been designed and fabricated for the evaluation of hot electron reliability. The differential Clapp-VCO is formed using cross-coupled nMOS transistors, on-chip transformers/inductors, and voltage-controlled capacitors. The experimental data demonstrate that the hot carrier damage increases the oscillation frequency and degrades the phase noise of Clapp-VCO.A p-channel transistor only VCO has been designed for low phase noise. The simulation results show that the phase noise degrades after NBTI stress at elevated temperature. This is due to increased interface states after NBTI stress. The process variability has also been evaluated.
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Date Issued: 2012
Identifier: CFE0004223, ucf:49000
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0004223

Title: Dynamic feedback pulse shaping for high power chirped pulse amplification system.
Creator: Nguyen, Dat, Delfyett, Peter, Rahman, Talat, Richardson, Martin, Schulzgen, Axel, Li, Guifang, University of Central Florida
Abstract / Description: The topic of this proposal is the development of high peak power laser sources with a focus on linearly chirped pulse laser sources. In the past decade chirped optical pulses have found a plethora of applications such as photonic analog-to-digital conversion, optical coherence tomography, laser ranging, etc. This dissertation analyzes the aforementioned applications of linearly chirped pulses and their technical requirements, as well as the performance of previously demonstrated parabolic...
Show moreThe topic of this proposal is the development of high peak power laser sources with a focus on linearly chirped pulse laser sources. In the past decade chirped optical pulses have found a plethora of applications such as photonic analog-to-digital conversion, optical coherence tomography, laser ranging, etc. This dissertation analyzes the aforementioned applications of linearly chirped pulses and their technical requirements, as well as the performance of previously demonstrated parabolic pulse shaping approaches. The experimental research addresses the topic of parabolic pulse generation in two distinct ways. First, pulse shaping technique involving a time domain approach is presented, that results in stretched pulses with parabolic profiles with temporal duration of 15 ns. After pulse is shaped into a parabolic intensity profile, the pulse is compressed with DCF fiber spool by 100 times to 80 ps duration at FWHM. A different approach of pulse shaping in frequency domain is performed, in which a spectral processor based on Liquid Crystal on Silicon technology is used. The pulse is stretched to 1.5 ns before intensity mask is applied, resulting in a parabolic intensity profile. Due to frequency to time mapping, its temporal profile is also parabolic. After pulse shaping, the pulse is compressed with a bulk compressor, and subsequently analyzed with a Frequency Resolved Optical Gating (FROG). The spectral content of the compressed pulse is feedback to the spectral processor and used to adjust the spectral phase mask applied on the pulse. The resultant pulse after pulse shaping with feedback mechanism is a Fourier transform, sub-picosecond ultrashort pulse with 5 times increase in peak power.The appendices in this dissertation provide additional material used for the realization of the main research focus of the dissertation. Specification and characterization of major components of equipment and devices used in the experiment are present. The description of Matlab algorithms that was used to calculate required signals for pulse shaping are shown. A brief description of the Labview code used to control the spectral processor will also be illustrated.
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Date Issued: 2013
Identifier: CFE0004899, ucf:49642
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0004899

Title: rf power amplifier and oscillator design for reliability and variability.
Creator: Chen, Shuyu, Yuan, Jiann-Shiun, Sundaram, Kalpathy, Shen, Zheng, Gong, Xun, Wang, Morgan, University of Central Florida
Abstract / Description: CMOS RF circuit design has been an ever-lasting research field. It gained so much attention since RF circuits have high mobility and wide band efficiency, while CMOS technology has the advantage of low cost and better capability of integration. At the same time, IC circuits never stopped scaling down for the recent many decades. Reliability issues with RF circuits have become more and more severe with device scaling down: reliability effects such as gate oxide break down, hot carrier...
Show moreCMOS RF circuit design has been an ever-lasting research field. It gained so much attention since RF circuits have high mobility and wide band efficiency, while CMOS technology has the advantage of low cost and better capability of integration. At the same time, IC circuits never stopped scaling down for the recent many decades. Reliability issues with RF circuits have become more and more severe with device scaling down: reliability effects such as gate oxide break down, hot carrier injection, negative bias temperature instability, have been amplified as the device size shrinks. Process variability issues also become more predominant as the feature size decreases. With these insights provided, reliability and variability evaluations on typical RF circuits and possible compensation techniques are highly desirable.In this work, a class E power amplifier is designed and laid out using TSMC 0.18 (&)#181;m RF technology and the chip was fabricated. Oxide stress and hot electron tests were carried out at elevated supply voltage, fresh measurement results were compared with different stress conditions after 10 hours. Test results matched very well with mixed mode circuit simulations, proved that hot carrier effects degrades PA performances like output power, power efficiency, etc. Self- heating effects were examined on a class AB power amplifier since PA has high power operations. Device temperature simulation was done both in DC and mixed mode level. Different gate biasing techniques were analyzed and their abilities to compensate output power were compared. A simple gate biasing circuit turned out to be efficient to compensate self-heating effects under different localized heating situations. Process variation was studied on a classic Colpitts oscillator using Monte-Carlo simulation. Phase noise was examined since it is a key parameter in oscillator. Phase noise was modeled using analytical equations and supported by good match between MATLAB results and ADS simulation. An adaptive body biasing circuit was proposed to eliminate process variation. Results from probability density function simulation demonstrated its capability to relieve process variation on phase noise. Standard deviation of phase noise with adaptive body bias is much less than the one without compensation. Finally, a robust, adaptive design technique using PLL as on-chip sensor to reduce Process, Voltage, Temperature (P.V.T.) variations and other aging effects on RF PA was evaluated. The frequency and phase of ring oscillator need to be adjusted to follow the frequency and phase of input in PLL no matter how the working condition varies. As a result, the control signal of ring oscillator has to fluctuate according to the working condition, reflecting the P.V.T changes. RF circuits suffer from similar P.V.T. variations. The control signal of PLL is introduced to RF circuits and converted to the adaptive tuning voltage for substrate bias. Simulation results illustrate that the PA output power under different variations is more flat than the one with no compensation. Analytical equations show good support to what has been observed.
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Date Issued: 2013
Identifier: CFE0004664, ucf:49894
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0004664

Title: CLASS-E CASCODE POWER AMPLIFIER ANALYSIS AND DESIGN FOR LONG TERM RELIABILITY.
Creator: Kutty, Karan, Yuan, Jiann-Shiun, University of Central Florida
Abstract / Description: This study investigated the Class-E power amplifier operating at 5.2 GHz. Since the operation of this amplifier applies a lot of stress on the switching transistor, a cascode topology was applied in order to reduce the drain-source voltage stress. Such an amplifier was designed and optimized in order to improve stability, power added efficiency, and matching. A layout for the said design was then created to be fabrication-ready using the TSMC 0.18 um technology. Post-layout simulations were...
Show moreThis study investigated the Class-E power amplifier operating at 5.2 GHz. Since the operation of this amplifier applies a lot of stress on the switching transistor, a cascode topology was applied in order to reduce the drain-source voltage stress. Such an amplifier was designed and optimized in order to improve stability, power added efficiency, and matching. A layout for the said design was then created to be fabrication-ready using the TSMC 0.18 um technology. Post-layout simulations were performed in order to realize a more realistic circuit performance with the layout design in mind. Long-term stress effects, such as oxide breakdown, on the key transistors were modeled and simulated in order to achieve an understanding of how leakage currents affect the overall circuit performance. Simulated results were compared and contrasted against theoretical understanding using derived equations. Recommendations for future advancements were made for modification and optimization of the circuit by the application of other stress reduction strategies, variation in the class-E topology, and improvement of the driver stage.
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Date Issued: 2010
Identifier: CFE0003360, ucf:48477
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003360

Title: CMOS RF CITUITS VARIABILITY AND RELIABILITY RESILIENT DESIGN, MODELING, AND SIMULATION.
Creator: Liu, Yidong, Yuan, Jiann-Shiun, University of Central Florida
Abstract / Description: The work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm...
Show moreThe work presents a novel voltage biasing design that helps the CMOS RF circuits resilient to variability and reliability. The biasing scheme provides resilience through the threshold voltage (VT) adjustment, and at the mean time it does not degrade the PA performance. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. Power Amplifier (PA) and Low Noise Amplifier (LNA) are investigated case by case through modeling and experiment. PTM 65nm technology is adopted in modeling the transistors within these RF blocks. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. Analytical equations are established for sensitivity of the resilient biasing under various scenarios. A traditional class-AB PA with resilient design is compared the same PA without such design in PTM 65nm technology. The results show that the biasing design helps improve the robustness of the PA in terms of linear gain, P1dB, Psat, and power added efficiency (PAE). Except for post-fabrication calibration capability, the design reduces the majority performance sensitivity of PA by 50% when subjected to threshold voltage (VT) shift and 25% to electron mobility (¼n) degradation. The impact of degradation mismatches is also investigated. It is observed that the accelerated aging of MOS transistor in the biasing circuit will further reduce the sensitivity of PA. In the study of LNA, a 24 GHz narrow band cascade LNA with adaptive biasing scheme under various aging rate is compared to LNA without such biasing scheme. The modeling and simulation results show that the adaptive substrate biasing reduces the sensitivity of noise figure and minimum noise figure subject to process variation and device aging such as threshold voltage shift and electron mobility degradation. Simulation of different aging rate also shows that the sensitivity of LNA is further reduced with the accelerated aging of the biasing circuit. Thus, for majority RF transceiver circuits, the adaptive body biasing scheme provides overall performance resilience to the device reliability induced degradation. Also the tuning ability designed in RF PA and LNA provides the circuit post-process calibration capability.
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Date Issued: 2011
Identifier: CFE0003595, ucf:48861
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003595

Title: CLASS F AND INVERSE CLASS F POWER AMPLIFIER SUBJECT TO ELECTRICAL STRESS EFFECT.
Creator: Skaria, Giji, Yuan, Jiann, University of Central Florida
Abstract / Description: This study investigated the Class F and inverse Class F RF power amplifier operating at 5.8 GHz. The major challenging issue in design and implementation of CMOS power transistor is the breakdown voltage especially in sub-micron CMOS technologies. In order to eliminate this problem a Cascode topologies were implemented to reduce the Drain-to-Source voltage (stress). A Cascode Class F & Inverse Class F RF power amplifier were designed, and optimized in order to improve efficiency and...
Show moreThis study investigated the Class F and inverse Class F RF power amplifier operating at 5.8 GHz. The major challenging issue in design and implementation of CMOS power transistor is the breakdown voltage especially in sub-micron CMOS technologies. In order to eliminate this problem a Cascode topologies were implemented to reduce the Drain-to-Source voltage (stress). A Cascode Class F & Inverse Class F RF power amplifier were designed, and optimized in order to improve efficiency and reliability using 0.18[micro]m CMOS technology process. A 50% decrease in the stress has been achieved in the Cascode class-F and Inverse class F amplifiers. The sensitivity and temperature effect were investigated using BSIM-4 model. Such an amplifier was designed and optimized for a good sensitivity. A substrate bias circuit was implemented to achieve a good sensitivity. Recommendations were made for future advancements for modification and optimization of the class F and inverse class F circuit by the application of other stress reduction strategies, and improvement of the substrate bias circuit for a better sensitivity.
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Date Issued: 2011
Identifier: CFE0004030, ucf:49161
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0004030

Title: Towards Energy-Efficient and Reliable Computing: From Highly-Scaled CMOS Devices to Resistive Memories.
Creator: Salehi Mobarakeh, Soheil, DeMara, Ronald, Fan, Deliang, Turgut, Damla, University of Central Florida
Abstract / Description: The continuous increase in transistor density based on Moore's Law has led us to highly scaled Complementary Metal-Oxide Semiconductor (CMOS) technologies. These transistor-based process technologies offer improved density as well as a reduction in nominal supply voltage. An analysis regarding different aspects of 45nm and 15nm technologies, such as power consumption and cell area to compare these two technologies is proposed on an IEEE 754 Single Precision Floating-Point Unit implementation....
Show moreThe continuous increase in transistor density based on Moore's Law has led us to highly scaled Complementary Metal-Oxide Semiconductor (CMOS) technologies. These transistor-based process technologies offer improved density as well as a reduction in nominal supply voltage. An analysis regarding different aspects of 45nm and 15nm technologies, such as power consumption and cell area to compare these two technologies is proposed on an IEEE 754 Single Precision Floating-Point Unit implementation. Based on the results, using the 15nm technology offers 4-times less energy and 3-fold smaller footprint. New challenges also arise, such as relative proportion of leakage power in standby mode that can be addressed by post-CMOS technologies. Spin-Transfer Torque Random Access Memory (STT-MRAM) has been explored as a post-CMOS technology for embedded and data storage applications seeking non-volatility, near-zero standby energy, and high density. Towards attaining these objectives for practical implementations, various techniques to mitigate the specific reliability challenges associated with STT-MRAM elements are surveyed, classified, and assessed herein. Cost and suitability metrics assessed include the area of nanomagmetic and CMOS components per bit, access time and complexity, Sense Margin (SM), and energy or power consumption costs versus resiliency benefits. In an attempt to further improve the Process Variation (PV) immunity of the Sense Amplifiers (SAs), a new SA has been introduced called Adaptive Sense Amplifier (ASA). ASA can benefit from low Bit Error Rate (BER) and low Energy Delay Product (EDP) by combining the properties of two of the commonly used SAs, Pre-Charge Sense Amplifier (PCSA) and Separated Pre-Charge Sense Amplifier (SPCSA). ASA can operate in either PCSA or SPCSA mode based on the requirements of the circuit such as energy efficiency or reliability. Then, ASA is utilized to propose a novel approach to actually leverage the PV in Non-Volatile Memory (NVM) arrays using Self-Organized Sub-bank (SOS) design. SOS engages the preferred SA alternative based on the intrinsic as-built behavior of the resistive sensing timing margin to reduce the latency and power consumption while maintaining acceptable access time.
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Date Issued: 2016
Identifier: CFE0006493, ucf:51400
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006493

Title: Broad Bandwidth, All-fiber, Thulium-doped Photonic Crystal Fiber Amplifier for Potential Use in Scaling Ultrashort Pulse Peak Powers.
Creator: Sincore, Alex, Richardson, Martin, Shah, Lawrence, Amezcua Correa, Rodrigo, University of Central Florida
Abstract / Description: Fiber based ultrashort pulse laser sources are desirable for many applications; however generating high peak powers in fiber lasers is primarily limited by the onset of nonlinear effects such as self-phase modulation, stimulated Raman scattering, and self-focusing. Increasing the fiber core diameter mitigates the onset of these nonlinear effects, but also allows unwanted higher-order transverse spatial modes to propagate. Both large core diameters and single-mode propagation can be...
Show moreFiber based ultrashort pulse laser sources are desirable for many applications; however generating high peak powers in fiber lasers is primarily limited by the onset of nonlinear effects such as self-phase modulation, stimulated Raman scattering, and self-focusing. Increasing the fiber core diameter mitigates the onset of these nonlinear effects, but also allows unwanted higher-order transverse spatial modes to propagate. Both large core diameters and single-mode propagation can be simultaneously attained using photonic crystal fibers.Thulium-doped fiber lasers are attractive for high peak power ultrashort pulse systems. They offer a broad gain bandwidth, capable of amplifying sub-100 femtosecond pulses. The longer center wavelength at 2 ?m theoretically enables higher peak powers relative to 1 ?m systems since nonlinear effects inversely scale with wavelength. Also, the 2 ?m emission is desirable to support applications reaching further into the mid-IR.This work evaluates the performance of a novel all-fiber pump combiner that incorporates a thulium-doped photonic crystal fiber. This fully integrated amplifier is characterized and possesses a large gain bandwidth, essentially single-mode propagation, and high degree of polarization. This innovative all-fiber, thulium-doped photonic crystal fiber amplifier has great potential for enabling high peak powers in 2 ?m fiber systems; however the current optical-to-optical efficiency is low relative to similar free-space amplifiers. Further development and device optimization will lead to higher efficiencies and improved performance.
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Date Issued: 2014
Identifier: CFE0005260, ucf:50611
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0005260

power amplifier (3)	+ -
CMOS (2)	+ -
Reliability (2)	+ -
reliability (2)	+ -
0.18[micro]m (1)	+ -

2 ?m (1)	+ -
2 micron (1)	+ -
Amplifier (1)	+ -
Cascode-Class F (1)	+ -
Class F (1)	+ -
Coupling Unit (1)	+ -
Design for reliability (1)	+ -
ESD (1)	+ -
Energy Efficient (1)	+ -
Fiber Amplifier (1)	+ -
Fiber Laser (1)	+ -
Gate-Drain Resistance (1)	+ -
Hot electron (1)	+ -
Inverse-class F (1)	+ -
Low Power (1)	+ -
Magnetic Tunnel Junction (MTJ) (1)	+ -
Master Oscillator Power Amplifier (1)	+ -
Monte Carlo simulation (1)	+ -
PCF (1)	+ -
Photonic Crystal Fiber (1)	+ -
Photonic crystal fiber (1)	+ -
Power Amplifier (1)	+ -
Power Line Communications (1)	+ -
Process Variation (1)	+ -
RF (1)	+ -

University of Central Florida (11)	+ -
Yuan, Jiann-Shiun (4)	+ -
Richardson, Martin (3)	+ -
Amezcua Correa, Rodrigo (2)	+ -
Shah, Lawrence (2)	+ -

Sundaram, Kalpathy (2)	+ -
Yuan, Jiann (2)	+ -
Chen, Shuyu (1)	+ -
Chow, Lee (1)	+ -
DeMara, Ronald (1)	+ -
Delfyett, Peter (1)	+ -
Fan, Deliang (1)	+ -
Gaida, Christian (1)	+ -
Gong, Xun (1)	+ -
Kutty, Karan (1)	+ -
Li, Guifang (1)	+ -
Liu, Yidong (1)	+ -
Narasimha Raju, Divya (1)	+ -
Nguyen, Dat (1)	+ -
Rahman, Talat (1)	+ -
Salehi Mobarakeh, Soheil (1)	+ -
Schulzgen, Axel (1)	+ -
Shen, Zheng (1)	+ -
Sincore, Alex (1)	+ -
Skaria, Giji (1)	+ -
Srinivasan, Bharath (1)	+ -
Tang, Hongxia (1)	+ -
Turgut, Damla (1)	+ -
Wang, Morgan (1)	+ -
Wei, Lei (1)	+ -

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