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Title: DESIGN AND ANALYSIS OF ADAPTIVE AND RECONFIGURABLE ANTENNAS FOR WIRELESS COMMUNICATION.
Creator: Ali, Maha Abdelmoneim, Wahid, Parveen, University of Central Florida
Abstract / Description: Modern radar and communication systems have experienced a tremendous increase in the number of antennas onboard, on the ground, and in orbital space. This places a burden due to the confined volume and limited weight requirements especially in space applications. The reconfigurable antenna is a promising and exciting new type of antenna, where through the use of appropriate switches the antenna can be structurally reconfigured, to maintain the elements near their resonant dimensions for...
Show moreModern radar and communication systems have experienced a tremendous increase in the number of antennas onboard, on the ground, and in orbital space. This places a burden due to the confined volume and limited weight requirements especially in space applications. The reconfigurable antenna is a promising and exciting new type of antenna, where through the use of appropriate switches the antenna can be structurally reconfigured, to maintain the elements near their resonant dimensions for several frequency bands. This increases the bandwidth of the antenna dramatically, which enables the use of one antenna for several applications. Four novel reconfigurable antenna elements were designed to work at 2.45 GHz and at 5.78 GHz, to cover the transition period when wireless communication will shift to the 5.78 GHz band. The four elements designed are: the reconfigurable Yagi, the reconfigurable corner-fed triangular loop antenna, the reconfigurable center-fed equilateral triangular loop antenna and the reconfigurable rectangular-spiral antenna. None of these antennas have been reported in the literature. Simulation results for all four antennas were obtained using IE3D. Fabrication and measurements for the Yagi antenna was done and the measured results agree with simulations. All four antennas have very good performance with respect to the 3dB beamwidth and directivity. However the reconfigurable rectangular-spiral antenna is the most compact in size among all four antennas. It is (20 mm x 20 mm) in size. At 2.45 GHz it has a 3dB beamwidth of 870 and directivity of 6.47dB. As for the 5.78GHz frequency the 3dB beamwidth is 82.50 and the directivity is 7.16dB. This dissertation also introduces the use of reconfigurable antenna elements in adaptive arrays. An adaptive array that can null interference and direct its main lobe to the desired signal while being reconfigurable to maintain functionality at several frequency bands has the potential to revolutionize wireless communications in the future. Through several examples, at both the design frequencies, it is shown that the reconfigurable and adaptive antenna arrays are successful in nulling noises incident on the array. These examples illustrate how reconfigurable elements and adaptive arrays can be combined very beneficially for use in wireless communication systems.
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Date Issued: 2004
Identifier: CFE0000003, ucf:46147
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0000003

Title: Enhancement of Antenna Array Performance Using Reconfigurable Slot-Ring Antennas and Integrated Filter/Antennas.
Creator: Li, Tianjiao, Gong, Xun, Wahid, Parveen, Yuan, Jiann-Shiun, Abdolvand, Reza, Kuebler, Stephen, University of Central Florida
Abstract / Description: As modern communication system technology develops, the demand for devices with smaller size, higher efficiency, and more functionality has increased dramatically. In addition, highly integrated RF-front-end modules with a reduced footprint and less transition loss between cascaded devices are desirable in most advanced wireless communication systems. Antenna arrays are widely used in wireless communication systems due to their high directivity and beam steering capability. Moreover, antenna...
Show moreAs modern communication system technology develops, the demand for devices with smaller size, higher efficiency, and more functionality has increased dramatically. In addition, highly integrated RF-front-end modules with a reduced footprint and less transition loss between cascaded devices are desirable in most advanced wireless communication systems. Antenna arrays are widely used in wireless communication systems due to their high directivity and beam steering capability. Moreover, antenna arrays are preferred in mobile communication systems for diversity reception to reduce signal fading effects. In order to meet the various requirements of rapidly developing wireless communication systems, low cost, compact, multifunctional integrated antenna arrays are in high demand.Reconfigurable antennas that can flexibly adapt to different applications by dynamically changing their frequency and radiation properties have attracted a lot of attention. Frequency, radiation pattern, polarization, or a combination of two or more of these parameters in the reconfiguration of antennas was studied and presented in recent years. A single reconfigurable antenna is able to replace multiple traditional antennas and accomplish different tasks. Thus, the complexity of wireless communication systems can be greatly reduced with a smaller device size. On the other hand, the integration of antennas with other devices in wireless communication systems that can improve the efficiency and shrink the device size is a growing trend in antenna technology. Compact and highly efficient integrated filters and antennas were studied previously; the studies show that by seamlessly co-designing filters with patch antennas, the fractional bandwidth (FBW) of the antennas can be enhanced as compared to stand-alone antennas.However, the advantages of both the reconfigurable antenna and integrated filter/antenna technology have not been fully applied to antenna array applications. Therefore, this dissertation explores how to maximize the antenna array performance using reconfigurable antennas and integrated filter/antennas. A continuously frequency reconfigurable slot-ring antenna/array with switches and varactors is presented first. By changing the state of the loaded switches, the reconfigurable slot-ring antenna/array is able to operate as an L-band slot-ring antenna or a 2(&)#215;2 S-band slot-ring antenna array. In each frequency band, the operation frequency of the antenna/array can be continuously tuned with the loaded varactors. To further enhance the functionality of the reconfigurable slot-ring antenna array, a dual-polarized fractal-shaped reconfigurable slot-ring antenna/array is developed with a reduced number of switches and an increased FBW. Additionally, ground plane solutions are explored to achieve single-sided radiation. The benefits of filter/antenna integration are also investigated in both linearly polarized patch phased arrays and circularly polarized patch antenna arrays. Finally, a preliminary study of a tunable integrated evanescent mode filter/antenna is conducted to validate the concept of combining reconfigurable antennas and integrated filter/antennas.
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Date Issued: 2017
Identifier: CFE0006950, ucf:51661
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006950

Title: RECONFIGURABLE COMPUTING FOR VIDEO CODING.
Creator: Huang, Jian, Lee, Jooheung, University of Central Florida
Abstract / Description: Video coding is widely used in our daily life. Due to its high computational complexity, hardware implementation is usually preferred. In this research, we investigate both ASIC hardware design approach and reconfigurable hardware design approach for video coding applications. First, we present a unified architecture that can perform Discrete Cosine Transform (DCT), Inverse Discrete Cosine Transform (IDCT), DCT domain motion estimation and compensation (DCT-ME/MC). Our proposed architecture...
Show moreVideo coding is widely used in our daily life. Due to its high computational complexity, hardware implementation is usually preferred. In this research, we investigate both ASIC hardware design approach and reconfigurable hardware design approach for video coding applications. First, we present a unified architecture that can perform Discrete Cosine Transform (DCT), Inverse Discrete Cosine Transform (IDCT), DCT domain motion estimation and compensation (DCT-ME/MC). Our proposed architecture is a Wavefront Array-based Processor with a highly modular structure consisting of 8*8 Processing Elements (PEs). By utilizing statistical properties and arithmetic operations, it can be used as a high performance hardware accelerator for video transcoding applications. We show how different core algorithms can be mapped onto the same hardware fabric and can be executed through the pre-defined PEs. In addition to the simplified design process of the proposed architecture and savings of the hardware resources, we also demonstrate that high throughput rate can be achieved for IDCT and DCT-MC by fully utilizing the sparseness property of DCT coefficient matrix. Compared to fixed hardware architecture using ASIC design approach, reconfigurable hardware design approach has higher flexibility, lower cost, and faster time-to-market. We propose a self-reconfigurable platform which can reconfigure the architecture of DCT computations during run-time using dynamic partial reconfiguration. The scalable architecture for DCT computations can compute different number of DCT coefficients in the zig-zag scan order to adapt to different requirements, such as power consumption, hardware resource, and performance. We propose a configuration manager which is implemented in the embedded processor in order to adaptively control the reconfiguration of scalable DCT architecture during run-time. In addition, we use LZSS algorithm for compression of the partial bitstreams and on-chip BlockRAM as a cache to reduce latency overhead for loading the partial bitstreams from the off-chip memory for run-time reconfiguration. A hardware module is designed for parallel reconfiguration of the partial bitstreams. The experimental results show that our approach can reduce the external memory accesses by 69% and can achieve 400 MBytes/s reconfiguration rate. Detailed trade-offs of power, throughput, and quality are investigated, and used as a criterion for self-reconfiguration. Prediction algorithm of zero quantized DCT (ZQDCT) to control the run-time reconfiguration of the proposed scalable architecture has been used, and 12 different modes of DCT computations including zonal coding, multi-block processing, and parallel-sequential stage modes are supported to reduce power consumptions, required hardware resources, and computation time with a small quality degradation. Detailed trade-offs of power, throughput, and quality are investigated, and used as a criterion for self-reconfiguration to meet the requirements set by the users.
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Date Issued: 2010
Identifier: CFE0003262, ucf:48522
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003262

Title: A COMPETITIVE RECONFIGURATION APPROACH TO AUTONOMOUS FAULT HANDLING USING GENETIC ALGORITHMS.
Creator: Zhang, Kening, DeMara, Ronald F, University of Central Florida
Abstract / Description: In this dissertation, a novel self-repair approach based on Consensus Based Evaluation (CBE) for autonomous repair of SRAM-based Field Programmable Gate Arrays (FPGAs) is developed, evaluated, and refined. An initial population of functionally identical (same input-output behavior), yet physically distinct (alternative design or place-and-route realization) FPGA configurations is produced at design time. During run-time, the CBE approach ranks these alternative configurations after evaluating...
Show moreIn this dissertation, a novel self-repair approach based on Consensus Based Evaluation (CBE) for autonomous repair of SRAM-based Field Programmable Gate Arrays (FPGAs) is developed, evaluated, and refined. An initial population of functionally identical (same input-output behavior), yet physically distinct (alternative design or place-and-route realization) FPGA configurations is produced at design time. During run-time, the CBE approach ranks these alternative configurations after evaluating their discrepancy relative to the consensus formed by the population. Through runtime competition, faults in the logical resources become occluded from the visibility of subsequent FPGA operations. Meanwhile, offspring formed through crossover and mutation of faulty and viable configurations are selected at a controlled re-introduction rate for evaluation and refurbishment. Refurbishments are evolved in-situ, with online real-time input-based performance evaluation, enhancing system availability and sustainability, creating an Organic Embedded System (OES). A fault tolerance model called N Modular Redundancy with Standby (NMRSB) is developed which combines the two popular fault tolerance techniques of NMR and Standby fault tolerance in order to facilitate the CBE approach. This dissertation develops two of instances of the NMRSB system – Triple Modular Redundancy with Standby (TMRSB) and Duplex with Standby (DSB). A hypothetical Xilinx Virtex-II Pro FPGA model demonstrates their viability for various applications including a 3-bit x 3-bit multiplier, and the MCNC91 benchmark circuits. Experiments conducted on the model iii evaluate the performance of three new genetic operators and demonstrate progress towards a completely self-contained single-chip implementation so that the FPGA can refurbish itself without requiring a PC host to execute the Genetic Algorithm. This dissertation presents results from the simulations of multiple applications with a CBE model implemented in the C++ programming language. Starting with an initial population of 20 and 30 viable configurations for TMRSB and DSB respectively, a single stuck-at fault is introduced in the logic resources. Fault refurbishment experiments are conducted under supervision of CBE using a fitness state evaluation function based on competing outputs, fitness adjustment, and different level threshold. The device remains online throughout the process by which a complete repair is realized with Hamming Distance and Bitweight voting schemes. The results indicate a Hamming Distance TMRSB approach can prevent the most pervasive fault impacts and realize complete refurbishment. Experimental results also show that the Autonomic Layer demonstrates 100% faulty component isolation for both Functional Elements (FEs) and Autonomous Elements (AEs) with randomly injected single and multiple faults. Using logic circuits from the MCNC-91 benchmark set, availability during repair phases averaged 75.05%, 82.21%, and 65.21% for the z4ml, cm85a, and cm138a circuits respectively under stated conditions. In addition to simulation, the proposed OES architecture synthesized from HDL was prototyped on a Xilinx Virtex II Pro FPGA device supporting partial reconfiguration to demonstrate the feasibility for intrinsic regeneration of the selected circuit.
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Date Issued: 2008
Identifier: CFE0002280, ucf:47849
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0002280

Title: RECONFIGURABLE ARCHITECTURE FOR H.264/AVC VARIABLE BLOCK SIZE MOTION ESTIMATION BASED ON MOTION ACTIVITY AND ADAPTIVE SEARCH RANGE.
Creator: Kodipyaka, Sumedha, Lee, Jooheung, University of Central Florida
Abstract / Description: Motion Estimation (ME) technique plays a key role in the video coding systems to achieve high compression ratios by removing temporal redundancies among video frames. Especially in the newest H.264/AVC video coding standard, ME engine demands large amount of computational capabilities due to its support for wide range of different block sizes for a given macroblock in order to increase accuracy in finding best matching block in the previous frames. We propose scalable architecture for H.264...
Show moreMotion Estimation (ME) technique plays a key role in the video coding systems to achieve high compression ratios by removing temporal redundancies among video frames. Especially in the newest H.264/AVC video coding standard, ME engine demands large amount of computational capabilities due to its support for wide range of different block sizes for a given macroblock in order to increase accuracy in finding best matching block in the previous frames. We propose scalable architecture for H.264/AVC Variable Block Size (VBS) Motion Estimation with adaptive computing capability to support various search ranges, input video resolutions, and frame rates. Hardware architecture of the proposed ME consists of scalable Sum of Absolute Difference (SAD) arrays which can perform Full Search Block Matching Algorithm (FSBMA) for smaller 4x4 blocks. It is also shown that by predicting motion activity and adaptively adjusting the Search Range (SR) on the reconfigurable hardware platform, the computational cost of ME required for inter-frame encoding in H.264/AVC video coding standard can be reduced significantly. Dynamic Partial Reconfiguration is a unique feature of Field Programmable Gate Arrays (FPGAs) that makes best use of hardware resources and power by allowing adaptive algorithm to be implemented during run-time. We exploit this feature of FPGA to implement the proposed reconfigurable architecture of ME and maximize the architectural benefits through prediction of motion activities in the video sequences ,adaptation of SR during run-time, and fractional ME refinement. The implemented ME architecture can support real time applications at a maximum frequency of 90MHz with multiple reconfigurable regions. When compared to reconfiguration of complete design, partial reconfiguration process results in smaller bitstream size which allows FPGA to implement different configurations at higher speed. The proposed architecture has modular structure, regular data flow, and efficient memory organization with lower memory accesses. By increasing the number of active partial reconfigurable modules from one to four, there is a 4 fold increase in data re-use. Also, by introducing adaptive SR reduction algorithm at frame level, the computational load of ME is reduced significantly with only small degradation in PSNR (0.1dB).
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Date Issued: 2010
Identifier: CFE0003316, ucf:48488
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003316

Title: BIT-RATE AWARE RECONFIGURABLE ARCHITECTURE FOR H.264/AVC DEBLOCKING FILTER.
Creator: Khraisha, Rakan, Lee, Jooheung, University of Central Florida
Abstract / Description: In H.264/AVC, DeBlocking Filter (DBF) achieves bit rate savings and it is used to improve visual quality by reducing the presence of blocking artifacts. However, these advantages come at the expense of increasing computational complexity of the DBF due to highly adaptive mode decision and small 4x4 block size. The DBF easily accounts for one third of the computational complexity of the decoder. The computational complexity required for various target applications from mobile to high...
Show moreIn H.264/AVC, DeBlocking Filter (DBF) achieves bit rate savings and it is used to improve visual quality by reducing the presence of blocking artifacts. However, these advantages come at the expense of increasing computational complexity of the DBF due to highly adaptive mode decision and small 4x4 block size. The DBF easily accounts for one third of the computational complexity of the decoder. The computational complexity required for various target applications from mobile to high definition video applications varies significantly. Therefore, it becomes apparent to design efficient architecture to adapt to different requirements. In this work, we exploit the scalability on both the hardware level and the algorithmic level to synergize the performance and to reduce computational complexity. First, we propose a modular DBF architecture which can be scaled to adapt to the required computing capability for various bit-rates, resolutions, and frame rates of video sequences. The scalable architecture is based on FPGA using dynamic partial reconfiguration. This desirable feature of FPGAs makes it possible for different hardware configurations to be implemented during run-time. The proposed design can be scaled to filter up to four different edges simultaneously, resulting in significant reduction of total processing time. Secondly, our experiments show by lowering the bit rate of video sequences, significant reduction in computational complexity can be achieved by the increased presence of skipped macroblocks, thus, avoiding redundant filtering operations. The implemented architecture has been evaluated using Xilinx Virtex-4 ML410 FPGA board. The design can operate at a maximum frequency of 103 MHz. The reconfiguration is done through Internal Configuration Access Port (ICAP) to achieve maximum performance needed by real time applications.
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Date Issued: 2010
Identifier: CFE0003247, ucf:48542
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003247

Title: A NOVEL EXPERIMENTAL APPROACH USING A RECONFIGURABLE TEST SETUP FOR COMPLEX NONLINEAR DYNAMIC SYSTEMS.
Creator: Rank, Aaron, Yun, Hae-Bum, University of Central Florida
Abstract / Description: Experimental nonlinear dynamics is an important area of study in the modern engineering field, with engineering applications in structural dynamics, structural control, and structural health monitoring. As a result, the discipline has experienced a great influx of research efforts to develop a versatile and reliable experimental methodology. A technical challenge in many experimental studies is the procurement of a device that exhibits the desired nonlinear behavior. As a result, many...
Show moreExperimental nonlinear dynamics is an important area of study in the modern engineering field, with engineering applications in structural dynamics, structural control, and structural health monitoring. As a result, the discipline has experienced a great influx of research efforts to develop a versatile and reliable experimental methodology. A technical challenge in many experimental studies is the procurement of a device that exhibits the desired nonlinear behavior. As a result, many researchers have longed for a versatile, but accurate, testing methodology that has complete freedom to simulate a wide range of nonlinearities and stochastic behaviors. The objective of this study is to develop a reconfigurable test setup as a tool to be used in a wide range of nonlinear dynamic studies. The main components include a moving mass whose restoring force can accurately be controlled and reprogrammed (with software) based upon measured displacement and velocity readings at each time step. The device offers control over nonlinear characteristics and the equation of dynamic motion. The advantage of having such an experimental setup is the ability to simulate various types of nonlinearities with the same test setup. As a result, the data collected can be used to help validate nonlinear modeling, system identification, and stochastic analysis studies. A physical test apparatus was developed, and various mechanical, electrical, and programming calibrations were performed for reliable experimental studies. To display potential uses for the reconfigurable approach, examples are presented where the device has been used to create physical data for use in change detection and deterioration studies. In addition, a demonstration is presented of the device's ability to physically simulate a large-scale orifice viscous damper, devices commonly used for vibration mitigation in bridges and buildings. For a large-scale viscous damper, physical testing is required to ensure structural design properties. However, due to the large scale of the dampers, expensive dynamic loading tests can be carried out at a very limited number of facilities. Using the reconfigurable test setup, the dynamic signature of the large-scale viscous damper can accurately be simulated with pre-collected data. The development of a system capable of emulating the restoring force of a nonlinear device with software is a novel approach and requires further calibration for increased reliability and accuracy. A discussion regarding the challenges faced when developing the methodology is presented and possible solutions are recommended. The methodology introduced by this apparatus is very promising. The device is a valuable experimental tool for researchers and designers, allowing for physical data collection, modeling, analysis, and validation of a wide class of nonlinear phenomena that commonly occur in a wide variety of engineering applications.
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Date Issued: 2011
Identifier: CFE0003982, ucf:48654
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003982

Title: A MULTI-LAYER FPGA FRAMEWORK SUPPORTING AUTONOMOUS RUNTIME PARTIAL RECONFIGURATION.
Creator: Tan, Heng, DeMara, Ronald, University of Central Florida
Abstract / Description: Partial reconfiguration is a unique capability provided by several Field Programmable Gate Array (FPGA) vendors recently, which involves altering part of the programmed design within an SRAM-based FPGA at run-time. In this dissertation, a Multilayer Runtime Reconfiguration Architecture (MRRA) is developed, evaluated, and refined for Autonomous Runtime Partial Reconfiguration of FPGA devices. Under the proposed MRRA paradigm, FPGA configurations can be manipulated at runtime using on-chip...
Show morePartial reconfiguration is a unique capability provided by several Field Programmable Gate Array (FPGA) vendors recently, which involves altering part of the programmed design within an SRAM-based FPGA at run-time. In this dissertation, a Multilayer Runtime Reconfiguration Architecture (MRRA) is developed, evaluated, and refined for Autonomous Runtime Partial Reconfiguration of FPGA devices. Under the proposed MRRA paradigm, FPGA configurations can be manipulated at runtime using on-chip resources. Operations are partitioned into Logic, Translation, and Reconfiguration layers along with a standardized set of Application Programming Interfaces (APIs). At each level, resource details are encapsulated and managed for efficiency and portability during operation. An MRRA mapping theory is developed to link the general logic function and area allocation information to the device related physical configuration level data by using mathematical data structure and physical constraints. In certain scenarios, configuration bit stream data can be read and modified directly for fast operations, relying on the use of similar logic functions and common interconnection resources for communication. A corresponding logic control flow is also developed to make the entire process autonomous. Several prototype MRRA systems are developed on a Xilinx Virtex II Pro platform. The Virtex II Pro on-chip PowerPC core and block RAM are employed to manage control operations while multiple physical interfaces establish and supplement autonomous reconfiguration capabilities. Area, speed and power optimization techniques are developed based on the developed Xilinx prototype. Evaluations and analysis of these prototype and techniques are performed on a number of benchmark and hashing algorithm case studies. The results indicate that based on a variety of test benches, up to 70% reduction in the resource utilization, up to 50% improvement in power consumption, and up to 10 times increase in run-time performance are achieved using the developed architecture and approaches compared with Xilinx baseline reconfiguration flow. Finally, a Genetic Algorithm (GA) for a FPGA fault tolerance case study is evaluated as a ultimate high-level application running on this architecture. It demonstrated that this is a hardware and software infrastructure that enables an FPGA to dynamically reconfigure itself efficiently under the control of a soft microprocessor core that is instantiated within the FPGA fabric. Such a system contributes to the observed benefits of intelligent control, fast reconfiguration, and low overhead.
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Date Issued: 2007
Identifier: CFE0001933, ucf:47448
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0001933

Title: Autonomous Recovery of Reconfigurable Logic Devices using Priority Escalation of Slack.
Creator: Imran, Syednaveed, DeMara, Ronald, Mikhael, Wasfy, Lin, Mingjie, Yuan, Jiann-Shiun, Geiger, Christopher, University of Central Florida
Abstract / Description: Field Programmable Gate Array (FPGA) devices offer a suitable platform for survivable hardware architectures in mission-critical systems. In this dissertation, active dynamic redundancy-based fault-handling techniques are proposed which exploit the dynamic partial reconfiguration capability of SRAM-based FPGAs. Self-adaptation is realized by employing reconfiguration in detection, diagnosis, and recovery phases.To extend these concepts to semiconductor aging and process variation in the deep...
Show moreField Programmable Gate Array (FPGA) devices offer a suitable platform for survivable hardware architectures in mission-critical systems. In this dissertation, active dynamic redundancy-based fault-handling techniques are proposed which exploit the dynamic partial reconfiguration capability of SRAM-based FPGAs. Self-adaptation is realized by employing reconfiguration in detection, diagnosis, and recovery phases.To extend these concepts to semiconductor aging and process variation in the deep submicron era, resilient adaptable processing systems are sought to maintain quality and throughput requirements despite the vulnerabilities of the underlying computational devices. A new approach to autonomous fault-handling which addresses these goals is developed using only a uniplex hardware arrangement. It operates by observing a health metric to achieve Fault Demotion using Reconfigurable Slack (FaDReS). Here an autonomous fault isolation scheme is employed which neither requires test vectors nor suspends the computational throughput, but instead observes the value of a health metric based on runtime input. The deterministic flow of the fault isolation scheme guarantees success in a bounded number of reconfigurations of the FPGA fabric.FaDReS is then extended to the Priority Using Resource Escalation (PURE) online redundancy scheme which considers fault-isolation latency and throughput trade-offs under a dynamic spare arrangement. While deep-submicron designs introduce new challenges, use of adaptive techniques are seen to provide several promising avenues for improving resilience. The scheme developed is demonstrated by hardware design of various signal processing circuits and their implementation on a Xilinx Virtex-4 FPGA device. These include a Discrete Cosine Transform (DCT) core, Motion Estimation (ME) engine, Finite Impulse Response (FIR) Filter, Support Vector Machine (SVM), and Advanced Encryption Standard (AES) blocks in addition to MCNC benchmark circuits. A significant reduction in power consumption is achieved ranging from 83% for low motion-activity scenes to 12.5% for high motion activity video scenes in a novel ME engine configuration. For a typical benchmark video sequence, PURE is shown to maintain a PSNR baseline near 32dB. The diagnosability, reconfiguration latency, and resource overhead of each approach is analyzed. Compared to previous alternatives, PURE maintains a PSNR within a difference of 4.02dB to 6.67dB from the fault-free baseline by escalating healthy resources to higher-priority signal processing functions. The results indicate the benefits of priority-aware resiliency over conventional redundancy approaches in terms of fault-recovery, power consumption, and resource-area requirements. Together, these provide a broad range of strategies to achieve autonomous recovery of reconfigurable logic devices under a variety of constraints, operating conditions, and optimization criteria.
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Date Issued: 2013
Identifier: CFE0005006, ucf:50005
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0005006

Title: OPTIMIZING DYNAMIC LOGIC REALIZATIONS FOR PARTIAL RECONFIGURATION OF FIELD PROGRAMMABLE GATE ARRAYS.
Creator: Parris, Matthew, DeMara, Ronald, University of Central Florida
Abstract / Description: Many digital logic applications can take advantage of the reconfiguration capability of Field Programmable Gate Arrays (FPGAs) to dynamically patch design flaws, recover from faults, or time-multiplex between functions. Partial reconfiguration is the process by which a user modifies one or more modules residing on the FPGA device independently of the others. Partial Reconfiguration reduces the granularity of reconfiguration to be a set of columns or rectangular region of the device....
Show moreMany digital logic applications can take advantage of the reconfiguration capability of Field Programmable Gate Arrays (FPGAs) to dynamically patch design flaws, recover from faults, or time-multiplex between functions. Partial reconfiguration is the process by which a user modifies one or more modules residing on the FPGA device independently of the others. Partial Reconfiguration reduces the granularity of reconfiguration to be a set of columns or rectangular region of the device. Decreasing the granularity of reconfiguration results in reduced configuration filesizes and, thus, reduced configuration times. When compared to one bitstream of a non-partial reconfiguration implementation, smaller modules resulting in smaller bitstream filesizes allow an FPGA to implement many more hardware configurations with greater speed under similar storage requirements. To realize the benefits of partial reconfiguration in a wider range of applications, this thesis begins with a survey of FPGA fault-handling methods, which are compared using performance-based metrics. Performance analysis of the Genetic Algorithm (GA) Offline Recovery method is investigated and candidate solutions provided by the GA are partitioned by age to improve its efficiency. Parameters of this aging technique are optimized to increase the occurrence rate of complete repairs. Continuing the discussion of partial reconfiguration, the thesis develops a case-study application that implements one partial reconfiguration module to demonstrate the functionality and benefits of time multiplexing and reveal the improved efficiencies of the latest large-capacity FPGA architectures. The number of active partial reconfiguration modules implemented on a single FPGA device is increased from one to eight to implement a dynamic video-processing architecture for Discrete Cosine Transform and Motion Estimation functions to demonstrate a 55-fold reduction in bitstream storage requirements thus improving partial reconfiguration capability.
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Date Issued: 2008
Identifier: CFE0002323, ucf:47793
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0002323

Title: BEAM-STEERABLE AND RECONFIGURABLE REFLECTARRAY ANTENNAS FOR HIGH GAIN SPACE APPLICATIONS.
Creator: Karnati, Kalyan, Gong, Xun, Wahid, Parveen, Jones, W Linwood, Wu, Thomas, Cho, Hyoung Jin, University of Central Florida
Abstract / Description: Reflectarray antennas uniquely combine the advantages of parabolic reflectors and phased array antennas. Comprised of planar structures similar to phased arrays and utilizing quasi-optical excitation similar to parabolic reflectors, reflectarray antennas provide beam steering without the need of complex and lossy feed networks. Chapter 1 discusses the basic theory of reflectarray and its design. A brief summary of previous work and current research status is also presented. The inherent...
Show moreReflectarray antennas uniquely combine the advantages of parabolic reflectors and phased array antennas. Comprised of planar structures similar to phased arrays and utilizing quasi-optical excitation similar to parabolic reflectors, reflectarray antennas provide beam steering without the need of complex and lossy feed networks. Chapter 1 discusses the basic theory of reflectarray and its design. A brief summary of previous work and current research status is also presented. The inherent advantages and drawbacks of the reflectarray are discussed.In chapter 2, a novel theoretical approach to extract the reflection coefficient of reflectarray unit cells is developed. The approach is applied to single-resonance unit cell elements under normal and waveguide incidences. The developed theory is also utilized to understand the difference between the TEM and TE10 mode of excitation. Using this theory, effects of different physical parameters on reflection properties of unit cells are studied without the need of full-wave simulations. Detailed analysis is performed for Ka-band reflectarray unit cells and verified by full-wave simulations. In addition, an approach to extract the Q factors using full-wave simulations is also presented. Lastly, a detailed study on the effects of inter-element spacing is discussed.Q factor theory discussed in chapter 2 is extended to account for the varying incidence angles and polarizations in chapter 3 utilizing Floquet modes. Emphasis is laid on elements located on planes where extremities in performance tend to occur. The antenna element properties are assessed in terms of maximum reflection loss and slope of the reflection phase. A thorough analysis is performed at Ka band and the results obtained are verified using full-wave simulations. Reflection coefficients over a 749-element reflectarray aperture for a broadside radiation pattern are presented for a couple of cases and the effects of coupling conditions in conjunction with incidence angles are demonstrated. The presented theory provides explicit physical intuition and guidelines for efficient and accurate reflectarray design.In chapter 4, tunable reflectarray elements capacitively loaded with Barium Strontium Titanate (BST) thin film are shown. The effects of substrate thickness, operating frequency and deposition pressure are shown utilizing coupling conditions and the performance is optimized. To ensure minimum affects from biasing, optimized biasing schemes are discussed. The proposed unit cells are fabricated and measured, demonstrating the reconfigurability by varying the applied E-field. To demonstrate the concept, a 45 element array is also designed and fabricated. Using anechoic chamber measurements, far-field patterns are obtained and a beam scan up to 25o is shown on the E-plane.Overall, novel theoretical approaches to analyze the reflection properties of the reflectarray elements using Q factors are developed. The proposed theoretical models provide valuable physical insight utilizing coupling conditions and aid in efficient reflectarray design. In addition, for the first time a continuously tunable reflectarray operating at Ka-band is presented using BST technology. Due to monolithic integration, the technique can be extended to higher frequencies such as V-band and above.
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Date Issued: 2015
Identifier: CFE0006040, ucf:50963
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006040

Title: Probabilistic-Based Computing Transformation with Reconfigurable Logic Fabrics.
Creator: Alawad, Mohammed, Lin, Mingjie, DeMara, Ronald, Mikhael, Wasfy, Wang, Jun, Das, Tuhin, University of Central Florida
Abstract / Description: Effectively tackling the upcoming (")zettabytes(") data explosion requires a huge quantum leapin our computing power and energy efficiency. However, with the Moore's law dwindlingquickly, the physical limits of CMOS technology make it almost intractable to achieve highenergy efficiency if the traditional (")deterministic and precise(") computing model still dominates.Worse, the upcoming data explosion mostly comprises statistics gleaned from uncertain,imperfect real-world environment. As such...
Show moreEffectively tackling the upcoming (")zettabytes(") data explosion requires a huge quantum leapin our computing power and energy efficiency. However, with the Moore's law dwindlingquickly, the physical limits of CMOS technology make it almost intractable to achieve highenergy efficiency if the traditional (")deterministic and precise(") computing model still dominates.Worse, the upcoming data explosion mostly comprises statistics gleaned from uncertain,imperfect real-world environment. As such, the traditional computing means of first-principlemodeling or explicit statistical modeling will very likely be ineffective to achieveflexibility, autonomy, and human interaction. The bottom line is clear: given where we areheaded, the fundamental principle of modern computing(-)deterministic logic circuits canflawlessly emulate propositional logic deduction governed by Boolean algebra(-)has to bereexamined, and transformative changes in the foundation of modern computing must bemade.This dissertation presents a novel stochastic-based computing methodology. It efficientlyrealizes the algorithmatic computing through the proposed concept of Probabilistic DomainTransform (PDT). The essence of PDT approach is to encode the input signal asthe probability density function, perform stochastic computing operations on the signal inthe probabilistic domain, and decode the output signal by estimating the probability densityfunction of the resulting random samples. The proposed methodology possesses manynotable advantages. Specifically, it uses much simplified circuit units to conduct complexoperations, which leads to highly area- and energy-efficient designs suitable for parallel processing.Moreover, it is highly fault-tolerant because the information to be processed isencoded with a large ensemble of random samples. As such, the local perturbations of itscomputing accuracy will be dissipated globally, thus becoming inconsequential to the final overall results. Finally, the proposed probabilistic-based computing can facilitate buildingscalable precision systems, which provides an elegant way to trade-off between computingaccuracy and computing performance/hardware efficiency for many real-world applications.To validate the effectiveness of the proposed PDT methodology, two important signal processingapplications, discrete convolution and 2-D FIR filtering, are first implemented andbenchmarked against other deterministic-based circuit implementations. Furthermore, alarge-scale Convolutional Neural Network (CNN), a fundamental algorithmic building blockin many computer vision and artificial intelligence applications that follow the deep learningprinciple, is also implemented with FPGA based on a novel stochastic-based and scalablehardware architecture and circuit design. The key idea is to implement all key componentsof a deep learning CNN, including multi-dimensional convolution, activation, and poolinglayers, completely in the probabilistic computing domain. The proposed architecture notonly achieves the advantages of stochastic-based computation, but can also solve severalchallenges in conventional CNN, such as complexity, parallelism, and memory storage.Overall, being highly scalable and energy efficient, the proposed PDT-based architecture iswell-suited for a modular vision engine with the goal of performing real-time detection, recognitionand segmentation of mega-pixel images, especially those perception-based computingtasks that are inherently fault-tolerant.
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Date Issued: 2016
Identifier: CFE0006828, ucf:51768
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006828

Title: Customizable Antenna Array Using Reconfigurable Antenna Elements.
Creator: Shirazi, Mahmoud, Gong, Xun, Wahid, Parveen, Jones, W Linwood, Abdolvand, Reza, Kuebler, Stephen, University of Central Florida
Abstract / Description: A shared-aperture reconfigurable slot-ring antenna array switching between different frequency bands and polarizations is presented for phased array applications. PIN diode switches are incorporated into the slots of the antenna to change the state of the reconfigurable slot-ring antenna array. Each frequency band has its own feeding lines which allows for the use of high-performance narrow-band transmit/receive (T/R) modules instead of ultra wideband (UWB) T/R modules. Furthermore, the...
Show moreA shared-aperture reconfigurable slot-ring antenna array switching between different frequency bands and polarizations is presented for phased array applications. PIN diode switches are incorporated into the slots of the antenna to change the state of the reconfigurable slot-ring antenna array. Each frequency band has its own feeding lines which allows for the use of high-performance narrow-band transmit/receive (T/R) modules instead of ultra wideband (UWB) T/R modules. Furthermore, the spacing between the elements in each frequency band is less than half free-space wavelength (?0) over the frequency band of operation which enables grating-lobe-free beam scanning. This is the first shared-aperture reconfigurable dual-polarized antenna with separate feeding for each band which is scalable to a larger array with element spacing of less than 0.5?0 in all frequency bands of operation.First, a switchable-band reconfigurable antenna array switching between L and C bands is presented. This antenna operates at 1.76/5.71 GHz with a fractional bandwidth (FBW) of 8.6%/11.5%, realized gain of 0.1/4.2 dBi and radiation efficiency of 66.6%/80.7% in the L-/C- band operating states, respectively. Second, a wideband version of the reconfigurable antenna element using fractal geometries is presented. This dual-polarized antenna element is switching between S and C bands with wide bandwidth in each operating state. In the S-/C-band operating state, this antenna shows 69.1%/58.3% FBW with a maximum realized gain of 2.4/3.1 dBi. Third, the wideband antenna element is extended to an antenna array. The reconfigurable dual-polarized antenna array with vertical coaxial feeding switches between S- and C-band states with full-band coverage. A 2(&)#215;2 S-band antenna array can be reconfigured to a 4(&)#215;4 C-band antenna array by activating/deactivating PIN diode switches. This antenna array shows 64.3%/66.7% FBW with 8.4/14.3 dBi maximum realized gain in the S-/C-band operating states, respectively. Finally, a reconfigurable antenna element covering three adjacent frequency bands is presented. The FBW of this tri-band antenna element is 75%/63%/26% in the S/C/X band state.
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Date Issued: 2018
Identifier: CFE0007373, ucf:52092
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007373

Title: Heterogeneous Reconfigurable Fabrics for In-circuit Training and Evaluation of Neuromorphic Architectures.
Creator: Mohammadizand, Ramtin, DeMara, Ronald, Lin, Mingjie, Sundaram, Kalpathy, Fan, Deliang, Wu, Annie, University of Central Florida
Abstract / Description: A heterogeneous device technology reconfigurable logic fabric is proposed which leverages the cooperating advantages of distinct magnetic random access memory (MRAM)-based look-up tables (LUTs) to realize sequential logic circuits, along with conventional SRAM-based LUTs to realize combinational logic paths. The resulting Hybrid Spin/Charge FPGA (HSC-FPGA) using magnetic tunnel junction (MTJ) devices within this topology demonstrates commensurate reductions in area and power consumption over...
Show moreA heterogeneous device technology reconfigurable logic fabric is proposed which leverages the cooperating advantages of distinct magnetic random access memory (MRAM)-based look-up tables (LUTs) to realize sequential logic circuits, along with conventional SRAM-based LUTs to realize combinational logic paths. The resulting Hybrid Spin/Charge FPGA (HSC-FPGA) using magnetic tunnel junction (MTJ) devices within this topology demonstrates commensurate reductions in area and power consumption over fabrics having LUTs constructed with either individual technology alone. Herein, a hierarchical top-down design approach is used to develop the HSC(&)#173; FPGA starting from the configurable logic block (CLB) and slice structures down to LUT circuits and the corresponding device fabrication paradigms. This facilitates a novel architectural approach to reduce leakage energy, minimize communication occurrence and energy cost by eliminating unnecessary data transfer, and support auto-tuning for resilience. Furthermore, HSC-FPGA enables new advantages of technology co-design which trades off alternative mappings between emerging devices and transistors at runtime by allowing dynamic remapping to adaptively leverage the intrinsic computing features of each device technology. HSC-FPGA offers a platform for fine-grained Logic-In-Memory architectures and runtime adaptive hardware.An orthogonal dimension of fabric heterogeneity is also non-determinism enabled by either low(&)#173; voltage CMOS or probabilistic emerging devices. It can be realized using probabilistic devices within a reconfigurable network to blend deterministic and probabilistic computational models. Herein, consider the probabilistic spin logic p-bit device as a fabric element comprising a crossbar(&)#173; structured weighted array. The programmability of the resistive network interconnecting p-bit devices can be achieved by modifying the resistive states of the array's weighted connections. Thus, the programmable weighted array forms a CLB-scale macro co-processing element with bitstream programmability. This allows field programmability for a wide range of classification problems and recognition tasks to allow fluid mappings of probabilistic and deterministic computing approaches. In particular, a Deep Belief Network (DBN) is implemented in the field using recurrent layers of co-processing elements to form an n(&)#215; m1(&)#215;m2(&)#215;...(&)#215;mi weighted array as a configurable hardware circuit with an n-input layer followed by i?1 hidden layers. As neuromorphic architectures using post-CMOS devices increase in capability and network size, the utility and benefits of reconfigurable fabrics of neuromorphic modules can be anticipated to continue to accelerate.
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Date Issued: 2019
Identifier: CFE0007502, ucf:52643
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0007502

Title: AN ADAPTIVE MODULAR REDUNDANCY TECHNIQUE TO SELF-REGULATE AVAILABILITY, AREA, AND ENERGY CONSUMPTION IN MISSION-CRITICAL APPLICATIONS.
Creator: Al-Haddad, Rawad, DeMara, Ronald, University of Central Florida
Abstract / Description: As reconfigurable devices' capacities and the complexity of applications that use them increase, the need for self-reliance of deployed systems becomes increasingly prominent. A Sustainable Modular Adaptive Redundancy Technique (SMART) composed of a dual-layered organic system is proposed, analyzed, implemented, and experimentally evaluated. SMART relies upon a variety of self-regulating properties to control availability, energy consumption, and area used, in dynamically-changing...
Show moreAs reconfigurable devices' capacities and the complexity of applications that use them increase, the need for self-reliance of deployed systems becomes increasingly prominent. A Sustainable Modular Adaptive Redundancy Technique (SMART) composed of a dual-layered organic system is proposed, analyzed, implemented, and experimentally evaluated. SMART relies upon a variety of self-regulating properties to control availability, energy consumption, and area used, in dynamically-changing environments that require high degree of adaptation. The hardware layer is implemented on a Xilinx Virtex-4 Field Programmable Gate Array (FPGA) to provide self-repair using a novel approach called a Reconfigurable Adaptive Redundancy System (RARS). The software layer supervises the organic activities within the FPGA and extends the self-healing capabilities through application-independent, intrinsic, evolutionary repair techniques to leverage the benefits of dynamic Partial Reconfiguration (PR). A SMART prototype is evaluated using a Sobel edge detection application. This prototype is shown to provide sustainability for stressful occurrences of transient and permanent fault injection procedures while still reducing energy consumption and area requirements. An Organic Genetic Algorithm (OGA) technique is shown capable of consistently repairing hard faults while maintaining correct edge detector outputs, by exploiting spatial redundancy in the reconfigurable hardware. A Monte Carlo driven Continuous Markov Time Chains (CTMC) simulation is conducted to compare SMART's availability to industry-standard Triple Modular Technique (TMR) techniques. Based on nine use cases, parameterized with realistic fault and repair rates acquired from publically available sources, the results indicate that availability is significantly enhanced by the adoption of fast repair techniques targeting aging-related hard-faults. Under harsh environments, SMART is shown to improve system availability from 36.02% with lengthy repair techniques to 98.84% with fast ones. This value increases to "five nines" (99.9998%) under relatively more favorable conditions. Lastly, SMART is compared to twenty eight standard TMR benchmarks that are generated by the widely-accepted BL-TMR tools. Results show that in seven out of nine use cases, SMART is the recommended technique, with power savings ranging from 22% to 29%, and area savings ranging from 17% to 24%, while still maintaining the same level of availability.
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Date Issued: 2011
Identifier: CFE0003993, ucf:48660
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0003993

Title: Design Disjunction for Resilient Reconfigurable Hardware.
Creator: Alzahrani, Ahmad, DeMara, Ronald, Yuan, Jiann-Shiun, Lin, Mingjie, Wang, Jun, Turgut, Damla, University of Central Florida
Abstract / Description: Contemporary reconfigurable hardware devices have the capability to achieve high performance, powerefficiency, and adaptability required to meet a wide range of design goals. With scaling challenges facing current complementary metal oxide semiconductor (CMOS), new concepts and methodologies supportingefficient adaptation to handle reliability issues are becoming increasingly prominent. Reconfigurable hardware and their ability to realize self-organization features are expected to play a key...
Show moreContemporary reconfigurable hardware devices have the capability to achieve high performance, powerefficiency, and adaptability required to meet a wide range of design goals. With scaling challenges facing current complementary metal oxide semiconductor (CMOS), new concepts and methodologies supportingefficient adaptation to handle reliability issues are becoming increasingly prominent. Reconfigurable hardware and their ability to realize self-organization features are expected to play a key role in designingfuture dependable hardware architectures. However, the exponential increase in density and complexity of current commercial SRAM-based field-programmable gate arrays (FPGAs) has escalated the overheadassociated with dynamic runtime design adaptation. Traditionally, static modular redundancy techniques areconsidered to surmount this limitation; however, they can incur substantial overheads in both area andpower requirements. To achieve a better trade-off among performance, area, power, and reliability, thisresearch proposes design-time approaches that enable fine selection of redundancy level based on target reliability goals and autonomous adaptation to runtime demands. To achieve this goal, three studies were conducted:First, a graph and set theoretic approach, named Hypergraph-Cover Diversity (HCD), is introduced as a preemptive design technique to shift the dominant costs of resiliency to design-time. In particular, union-freehypergraphs are exploited to partition the reconfigurable resources pool into highly separable subsets ofresources, each of which can be utilized by the same synthesized application netlist. The diverseimplementations provide reconfiguration-based resilience throughout the system lifetime while avoiding thesignificant overheads associated with runtime placement and routing phases. Evaluation on a Motion-JPEGimage compression core using a Xilinx 7-series-based FPGA hardware platform has demonstrated thepotential of the proposed FT method to achieve 37.5% area saving and up to 66% reduction in powerconsumption compared to the frequently-used TMR scheme while providing superior fault tolerance.Second, Design Disjunction based on non-adaptive group testing is developed to realize a low-overheadfault tolerant system capable of handling self-testing and self-recovery using runtime partial reconfiguration.Reconfiguration is guided by resource grouping procedures which employ non-linear measurements given by the constructive property of f-disjunctness to extend runtime resilience to a large fault space and realize a favorable range of tradeoffs. Disjunct designs are created using the mosaic convergence algorithmdeveloped such that at least one configuration in the library evades any occurrence of up to d resource faults, where d is lower-bounded by f. Experimental results for a set of MCNC and ISCAS benchmarks havedemonstrated f-diagnosability at the individual slice level with average isolation resolution of 96.4% (94.4%) for f=1 (f=2) while incurring an average critical path delay impact of only 1.49% and area cost roughly comparable to conventional 2-MR approaches. Finally, the proposed Design Disjunction method is evaluated as a design-time method to improve timing yield in the presence of large random within-die (WID) process variations for application with a moderately high production capacity.
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Date Issued: 2015
Identifier: CFE0006250, ucf:51086
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006250

Title: Optimal distribution network reconfiguration using meta-heuristic algorithms.
Creator: Asrari, Arash, Wu, Thomas, Lotfifard, Saeed, Haralambous, Michael, Atia, George, Pazour, Jennifer, University of Central Florida
Abstract / Description: Finding optimal configuration of power distribution systems topology is an NP-hard combinatorial optimization problem. It becomes more complex when time varying nature of loads in large-scale distribution systems is taken into account. In the second chapter of this dissertation, a systematic approach is proposed to tackle the computational burden of the procedure. To solve the optimization problem, a novel adaptive fuzzy based parallel genetic algorithm (GA) is proposed that employs the...
Show moreFinding optimal configuration of power distribution systems topology is an NP-hard combinatorial optimization problem. It becomes more complex when time varying nature of loads in large-scale distribution systems is taken into account. In the second chapter of this dissertation, a systematic approach is proposed to tackle the computational burden of the procedure. To solve the optimization problem, a novel adaptive fuzzy based parallel genetic algorithm (GA) is proposed that employs the concept of parallel computing in identifying the optimal configuration of the network. The integration of fuzzy logic into GA enhances the efficiency of the parallel GA by adaptively modifying the migration rates between different processors during the optimization process. A computationally efficient graph encoding method based on Dandelion coding strategy is developed which automatically generates radial topologies and prevents the construction of infeasible radial networks during the optimization process. The main shortcoming of the proposed algorithm in Chapter 2 is that it identifies only one single solution. It means that the system operator will not have any option but relying on the found solution. That is why a novel hybrid optimization algorithm is proposed in the third chapter of this dissertation that determines Pareto frontiers, as candidate solutions, for multi-objective distribution network reconfiguration problem. Implementing this model, the system operator will have more flexibility in choosing the best configuration among the alternative solutions. The proposed hybrid optimization algorithm combines the concept of fuzzy Pareto dominance (FPD) with shuffled frog leaping algorithm (SFLA) to recognize non-dominated suboptimal solutions identified by SFLA. The local search step of SFLA is also customized for power systems applications so that it automatically creates and analyzes only the feasible and radial configurations in its optimization procedure which significantly increases the convergence speed of the algorithm. In the fourth chapter, the problem of optimal network reconfiguration is solved for the case in which the system operator is going to employ an optimization algorithm that is automatically modifying its parameters during the optimization process. Defining three fuzzy functions, the probability of crossover and mutation will be adaptively tuned as the algorithm proceeds and the premature convergence will be avoided while the convergence speed of identifying the optimal configuration will not decrease. This modified genetic algorithm is considered a step towards making the parallel GA, presented in the second chapter of this dissertation, more robust in avoiding from getting stuck in local optimums. In the fifth chapter, the concentration will be on finding a potential smart grid solution to more high-quality suboptimal configurations of distribution networks. This chapter is considered an improvement for the third chapter of this dissertation for two reasons: (1) A fuzzy logic is used in the partitioning step of SFLA to improve the proposed optimization algorithm and to yield more accurate classification of frogs. (2) The problem of system reconfiguration is solved considering the presence of distributed generation (DG) units in the network. In order to study the new paradigm of integrating smart grids into power systems, it will be analyzed how the quality of suboptimal solutions can be affected when DG units are continuously added to the distribution network.The heuristic optimization algorithm which is proposed in Chapter 3 and is improved in Chapter 5 is implemented on a smaller case study in Chapter 6 to demonstrate that the identified solution through the optimization process is the same with the optimal solution found by an exhaustive search.
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Date Issued: 2015
Identifier: CFE0005575, ucf:50238
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0005575

Title: Adaptive Architectural Strategies for Resilient Energy-Aware Computing.
Creator: Ashraf, Rizwan, DeMara, Ronald, Lin, Mingjie, Wang, Jun, Jha, Sumit, Johnson, Mark, University of Central Florida
Abstract / Description: Reconfigurable logic or Field-Programmable Gate Array (FPGA) devices have the ability to dynamically adapt the computational circuit based on user-specified or operating-condition requirements. Such hardware platforms are utilized in this dissertation to develop adaptive techniques for achieving reliable and sustainable operation while autonomously meeting these requirements. In particular, the properties of resource uniformity and in-field reconfiguration via on-chip processors are exploited...
Show moreReconfigurable logic or Field-Programmable Gate Array (FPGA) devices have the ability to dynamically adapt the computational circuit based on user-specified or operating-condition requirements. Such hardware platforms are utilized in this dissertation to develop adaptive techniques for achieving reliable and sustainable operation while autonomously meeting these requirements. In particular, the properties of resource uniformity and in-field reconfiguration via on-chip processors are exploited to implement Evolvable Hardware (EHW). EHW utilize genetic algorithms to realize logic circuits at runtime, as directed by the objective function. However, the size of problems solved using EHW as compared with traditional approaches has been limited to relatively compact circuits. This is due to the increase in complexity of the genetic algorithm with increase in circuit size. To address this research challenge of scalability, the Netlist-Driven Evolutionary Refurbishment (NDER) technique was designed and implemented herein to enable on-the-fly permanent fault mitigation in FPGA circuits. NDER has been shown to achieve refurbishment of relatively large sized benchmark circuits as compared to related works. Additionally, Design Diversity (DD) techniques which are used to aid such evolutionary refurbishment techniques are also proposed and the efficacy of various DD techniques is quantified and evaluated.Similarly, there exists a growing need for adaptable logic datapaths in custom-designed nanometer-scale ICs, for ensuring operational reliability in the presence of Process, Voltage, and Temperature (PVT) and, transistor-aging variations owing to decreased feature sizes for electronic devices. Without such adaptability, excessive design guardbands are required to maintain the desired integration and performance levels. To address these challenges, the circuit-level technique of Self-Recovery Enabled Logic (SREL) was designed herein. At design-time, vulnerable portions of the circuit identified using conventional Electronic Design Automation tools are replicated to provide post-fabrication adaptability via intelligent techniques. In-situ timing sensors are utilized in a feedback loop to activate suitable datapaths based on current conditions that optimize performance and energy consumption. Primarily, SREL is able to mitigate the timing degradations caused due to transistor aging effects in sub-micron devices by reducing the stress induced on active elements by utilizing power-gating. As a result, fewer guardbands need to be included to achieve comparable performance levels which leads to considerable energy savings over the operational lifetime.The need for energy-efficient operation in current computing systems has given rise to Near-Threshold Computing as opposed to the conventional approach of operating devices at nominal voltage. In particular, the goal of exascale computing initiative in High Performance Computing (HPC) is to achieve 1 EFLOPS under the power budget of 20MW. However, it comes at the cost of increased reliability concerns, such as the increase in performance variations and soft errors. This has given rise to increased resiliency requirements for HPC applications in terms of ensuring functionality within given error thresholds while operating at lower voltages. My dissertation research devised techniques and tools to quantify the effects of radiation-induced transient faults in distributed applications on large-scale systems. A combination of compiler-level code transformation and instrumentation are employed for runtime monitoring to assess the speed and depth of application state corruption as a result of fault injection. Finally, fault propagation models are derived for each HPC application that can be used to estimate the number of corrupted memory locations at runtime. Additionally, the tradeoffs between performance and vulnerability and the causal relations between compiler optimization and application vulnerability are investigated.
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Date Issued: 2015
Identifier: CFE0006206, ucf:52889
Format: Document (PDF)
PURL: http://purl.flvc.org/ucf/fd/CFE0006206

FPGA (4)	+ -
Reconfigurable Computing (4)	+ -
Antennas (2)	+ -
Evolvable Hardware (2)	+ -
Fault-tolerance (2)	+ -

Reconfigurable antennas (2)	+ -
ASIC (1)	+ -
Adaptable Computer Architecture (1)	+ -
Adaptive (1)	+ -
Adaptive architectures (1)	+ -
Antenna (1)	+ -
Application Specific Integrated Circuit (ASIC) (1)	+ -
Application Vulnerability Characterization (1)	+ -
Array (1)	+ -
Arrays (1)	+ -
Autonomous recovery (1)	+ -
Availability (1)	+ -
BST (1)	+ -
Bias Temperature Instability (BTI) (1)	+ -
Bitstream Manipulation (1)	+ -
Common Mode Failure (CMF) (1)	+ -
Compiler Optimizations (1)	+ -
Convolution (1)	+ -
Convolutional Neural Network (1)	+ -
Coupling conditions (1)	+ -
DCT (1)	+ -
Deep Belief Network (DBN) (1)	+ -
Design Diversity (1)	+ -
Design Guardband (1)	+ -
Digital Circuit (1)	+ -

University of Central Florida (18)	+ -
DeMara, Ronald (8)	+ -
Lin, Mingjie (5)	+ -
Wahid, Parveen (4)	+ -
Gong, Xun (3)	+ -

Lee, Jooheung (3)	+ -
Wang, Jun (3)	+ -
Yuan, Jiann-Shiun (3)	+ -
Abdolvand, Reza (2)	+ -
Jones, W Linwood (2)	+ -
Kuebler, Stephen (2)	+ -
Mikhael, Wasfy (2)	+ -
Wu, Thomas (2)	+ -
Al-Haddad, Rawad (1)	+ -
Alawad, Mohammed (1)	+ -
Ali, Maha Abdelmoneim (1)	+ -
Alzahrani, Ahmad (1)	+ -
Ashraf, Rizwan (1)	+ -
Asrari, Arash (1)	+ -
Atia, George (1)	+ -
Cho, Hyoung Jin (1)	+ -
Das, Tuhin (1)	+ -
DeMara, Ronald F (1)	+ -
Fan, Deliang (1)	+ -
Geiger, Christopher (1)	+ -
Haralambous, Michael (1)	+ -
Huang, Jian (1)	+ -
Imran, Syednaveed (1)	+ -
Jha, Sumit (1)	+ -
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